公开(公告)号：US20060237850A1

公开(公告)日：2006-10-26

申请号：US11110283

申请日：2005-04-20

申请人： Yuan Yuan ,  Kevin Hess ,  Chu-Chung Lee ,  Tu-Anh Tran ,  Alan Woosley ,  Donna Woosley

发明人： Yuan Yuan ,  Kevin Hess ,  Chu-Chung Lee ,  Tu-Anh Tran ,  Alan Woosley ,  Donna Woosley

IPC分类号： H01L23/48

CPC分类号： H01L23/3185 ,  H01L21/78 ,  H01L23/3128 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An integrated circuit has a semiconductor substrate and an interconnect layer that mechanically relatively weak and susceptible to cracks and delamination. In the formation of the integrated circuit from a semiconductor wafer, a cut is made through the interconnect layer to form an edge of the interconnect layer. This cut may continue completely through the wafer thickness or stop short of doing so. In either case, after cutting through the interconnect layer, a reconditioning layer is formed on the edge of the interconnect layer. This reconditioning layer seals the existing cracks and delaminations and inhibits the further delamination or cracking of the interconnect layer. The sealing layer may be formed, for example, before the cut through the wafer, after the cut through the wafer but before any packaging, or after performing wirebonding between the interconnect layer and an integrated circuit package.

摘要翻译： 集成电路具有机械相对较弱并易于产生裂纹和分层的半导体衬底和互连层。 在从半导体晶片形成集成电路的过程中，通过互连层进行切割以形成互连层的边缘。 该切割可以完全延续晶片厚度，或者停止这样做。 在任一情况下，在切穿互连层之后，在互连层的边缘上形成再生层。 该修复层密封现有的裂纹和分层，并且抑制互连层的进一步分层或破裂。 密封层可以例如在经过晶片切割之后，经过晶片切割之后，但在任何包装之前，或者在互连层和集成电路封装之间进行引线键合之后形成。

公开(公告)号：US07049694B2

公开(公告)日：2006-05-23

申请号：US11270300

申请日：2005-11-09

申请人： Yaping Zhou ,  Chu-Chung Lee

发明人： Yaping Zhou ,  Chu-Chung Lee

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L24/85 ,  H01L23/49838 ,  H01L23/552 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05553 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45166 ,  H01L2224/45184 ,  H01L2224/45565 ,  H01L2224/45684 ,  H01L2224/48091 ,  H01L2224/48464 ,  H01L2224/49111 ,  H01L2224/4917 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/78 ,  H01L2924/00

摘要： A semiconductor package uses various forms of conductive traces that connect to die bond pads via bond wires. In one form, adjacent bond wires are intentionally crossed around midpoints thereof to reduce self-inductance of the conductors and to minimize self-inductance. In another form, bond wires associated with bond pads having intervening, unrelated bond pads are crossed. Additionally, conductive traces are divided into separate sections and electrically connected by crossed jumper wires or bond wires. Any number of separate sections may be formed for each trace, but an even number is preferable. In another form, one trace is continuous and divides a second trace into two or more sections. The multiple sections are connected by an overlying bond wire. Either insulated or non-insulated bond wire may be used.

公开(公告)号：US20060065966A1

公开(公告)日：2006-03-30

申请号：US11270300

申请日：2005-11-09

申请人： Yaping Zhou ,  Chu-Chung Lee

发明人： Yaping Zhou ,  Chu-Chung Lee

IPC分类号： H01L23/52

CPC分类号： H01L24/85 ,  H01L23/49838 ,  H01L23/552 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05553 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45166 ,  H01L2224/45184 ,  H01L2224/45565 ,  H01L2224/45684 ,  H01L2224/48091 ,  H01L2224/48464 ,  H01L2224/49111 ,  H01L2224/4917 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/78 ,  H01L2924/00

摘要： A semiconductor package uses various forms of conductive traces that connect to die bond pads via bond wires. In one form, adjacent bond wires are intentionally crossed around midpoints thereof to reduce self-inductance of the conductors and to minimize self-inductance. In another form, bond wires associated with bond pads having intervening, unrelated bond pads are crossed. Additionally, conductive traces are divided into separate sections and electrically connected by crossed jumper wires or bond wires. Any number of separate sections may be formed for each trace, but an even number is preferable. In another form, one trace is continuous and divides a second trace into two or more sections. The multiple sections are connected by an overlying bond wire. Either insulated or non-insulated bond wire may be used.

公开(公告)号：US06992377B2

公开(公告)日：2006-01-31

申请号：US10787288

申请日：2004-02-26

申请人： Yaping Zhou ,  Chu-Chung Lee

发明人： Yaping Zhou ,  Chu-Chung Lee

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L24/85 ,  H01L23/49838 ,  H01L23/552 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05553 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45166 ,  H01L2224/45184 ,  H01L2224/45565 ,  H01L2224/45684 ,  H01L2224/48091 ,  H01L2224/48464 ,  H01L2224/49111 ,  H01L2224/4917 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/78 ,  H01L2924/00

摘要： A semiconductor package uses various forms of conductive traces that connect to die bond pads via bond wires. In one form, adjacent bond wires are intentionally crossed around midpoints thereof to reduce self-inductance of the conductors and to minimize self-inductance. In another form, bond wires associated with bond pads having intervening, unrelated bond pads are crossed. Additionally, conductive traces are divided into separate sections and electrically connected by crossed jumper wires or bond wires. Any number of separate sections may be formed for each trace, but an even number is preferable. In another form, one trace is continuous and divides a second trace into two or more sections. The multiple sections are connected by an overlying bond wire. Either insulated or non-insulated bond wire may be used.

公开(公告)号：US06937047B2

公开(公告)日：2005-08-30

申请号：US10634484

申请日：2003-08-05

申请人： Tu-Anh Tran ,  Richard K. Eguchi ,  Peter R. Harper ,  Chu-Chung Lee ,  William M. Williams ,  Lois Yong

发明人： Tu-Anh Tran ,  Richard K. Eguchi ,  Peter R. Harper ,  Chu-Chung Lee ,  William M. Williams ,  Lois Yong

IPC分类号： G01R31/28 ,  G01R31/317 ,  G01R31/3187 ,  G11C29/48 ,  G01R31/02

CPC分类号： G11C29/1201 ,  G01R31/2884 ,  G01R31/31715 ,  G01R31/3187 ,  G11C29/48 ,  H01L2224/05554

摘要： A semiconductor device has a large number of bond pads on the periphery for wirebonding. The semiconductor device has a module as well as other circuitry, but the module takes significantly longer to test than the other circuitry. A relatively small number of the bond pads, the module bond pads, are required for the module testing due, at least in part, to the semiconductor device having a built-in self-test (BIST) circuitry. The functionality of these module bond pads is duplicated on the top surface of and in the interior of the semiconductor device with module test pads that are significantly larger than the bond pads on the periphery. Having large pads for testing allows longer probe needles, thus increasing parallel testing capability. Duplicating the functionality is achieved through a test pad interface so that the module bond pads and the module test pads do not have to be shorted together.

摘要翻译： 半导体器件在外围具有大量用于引线键合的接合焊盘。 该半导体器件具有模块以及其他电路，但该模块比其他电路需要更长的测试时间。 由于至少部分地由具有内置自检（BIST）电路的半导体器件，模块测试需要相对较少数量的接合焊盘（模块接合焊盘）。 这些模块接合焊盘的功能在半导体器件的顶表面和内部复制，模块测试焊盘明显大于外围的焊盘。 具有大的测试垫可以延长探针，从而提高并行测试能力。 通过测试接口接口实现复制功能，使得模块接合焊盘和模块测试焊盘不必一起短路。

公开(公告)号：US20150084199A1

公开(公告)日：2015-03-26

申请号：US14557769

申请日：2014-12-02

申请人： Leo M. Higgins, III ,  Chu-Chung Lee

发明人： Leo M. Higgins, III ,  Chu-Chung Lee

IPC分类号： H01L23/00

CPC分类号： H01L24/48 ,  H01L24/05 ,  H01L24/45 ,  H01L24/49 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4845 ,  H01L2224/48451 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/48824 ,  H01L2224/49175 ,  H01L2224/85206 ,  H01L2224/85207 ,  H01L2224/859 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00

摘要： An integrated circuit wire bond connection is provided having an aluminum bond pad (51) that is directly bonded to a copper ball (52) to form an aluminum splash structure (53) and associated crevice opening (55) at a peripheral bond edge of the copper ball (54), where the aluminum splash structure (53) is characterized by a plurality of geometric properties indicative of a reliable copper ball bond, such as lateral splash size, splash shape, relative position of splash-ball crevice to the aluminum pad, crevice width, crevice length, crevice angle, and/or crevice-pad splash index.

摘要翻译： 提供集成电路引线接合连接，其具有直接结合到铜球（52）的铝接合焊盘（51），以在所述铝球的外围接合边缘处形成铝飞溅结构（53）和相关的缝隙开口（55） 铜球（54），其中铝飞溅结构（53）的特征在于表示可靠的铜球接合的多个几何特性，例如侧面飞溅尺寸，飞溅形状，飞溅球缝隙相对于铝垫的相对位置 ，缝隙宽度，缝隙长度，缝隙角度和/或缝隙喷溅指数。

公开(公告)号：US08907485B2

公开(公告)日：2014-12-09

申请号：US13594732

申请日：2012-08-24

申请人： Leo M. Higgins, III ,  Chu-Chung Lee

发明人： Leo M. Higgins, III ,  Chu-Chung Lee

IPC分类号： H01L23/49 ,  H01L21/607 ,  H01L21/603 ,  H01L23/485

CPC分类号： H01L24/48 ,  H01L24/05 ,  H01L24/45 ,  H01L24/49 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4845 ,  H01L2224/48451 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/48824 ,  H01L2224/49175 ,  H01L2224/85206 ,  H01L2224/85207 ,  H01L2224/859 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00

摘要： An integrated circuit wire bond connection is provided having an aluminum bond pad (51) that is directly bonded to a copper ball (52) to form an aluminum splash structure (53) and associated crevice opening (55) at a peripheral bond edge of the copper ball (54), where the aluminum splash structure (53) is characterized by a plurality of geometric properties indicative of a reliable copper ball bond, such as lateral splash size, splash shape, relative position of splash-ball crevice to the aluminum pad, crevice width, crevice length, crevice angle, and/or crevice-pad splash index.

摘要翻译： 提供集成电路引线接合连接，其具有直接结合到铜球（52）的铝接合焊盘（51），以在所述铝球的外围接合边缘处形成铝飞溅结构（53）和相关的缝隙开口（55） 铜球（54），其中铝飞溅结构（53）的特征在于表示可靠的铜球接合的多个几何特性，例如侧面飞溅尺寸，飞溅形状，飞溅球缝隙相对于铝垫的相对位置 ，缝隙宽度，缝隙长度，缝隙角度和/或缝隙喷溅指数。

公开(公告)号：US20140054781A1

公开(公告)日：2014-02-27

申请号：US13594732

申请日：2012-08-24

申请人： Leo M. Higgins, III ,  Chu-Chung Lee

发明人： Leo M. Higgins, III ,  Chu-Chung Lee

IPC分类号： H01L23/49 ,  H01L21/607 ,  H01L21/603

CPC分类号： H01L24/48 ,  H01L24/05 ,  H01L24/45 ,  H01L24/49 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4845 ,  H01L2224/48451 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/48824 ,  H01L2224/49175 ,  H01L2224/85206 ,  H01L2224/85207 ,  H01L2224/859 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00

摘要： An integrated circuit wire bond connection is provided having an aluminum bond pad (51) that is directly bonded to a copper ball (52) to form an aluminum splash structure (53) and associated crevice opening (55) at a peripheral bond edge of the copper ball (54), where the aluminum splash structure (53) is characterized by a plurality of geometric properties indicative of a reliable copper ball bond, such as lateral splash size, splash shape, relative position of splash-ball crevice to the aluminum pad, crevice width, crevice length, crevice angle, and/or crevice-pad splash index.

摘要翻译： 提供集成电路引线接合连接，其具有直接结合到铜球（52）的铝接合焊盘（51），以在所述铝球的外围接合边缘处形成铝飞溅结构（53）和相关的缝隙开口（55） 铜球（54），其中铝飞溅结构（53）的特征在于表示可靠的铜球接合的多个几何特性，例如侧向飞溅尺寸，飞溅形状，飞溅球缝隙相对于铝垫的相对位置 ，缝隙宽度，缝隙长度，缝隙角度和/或缝隙喷溅指数。

公开(公告)号：US20120153464A1

公开(公告)日：2012-06-21

申请号：US13355748

申请日：2012-01-23

申请人： Kevin J. Hess ,  Chu-Chung Lee

发明人： Kevin J. Hess ,  Chu-Chung Lee

IPC分类号： H01L23/485 ,  H01B5/00

CPC分类号： H01L24/85 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/1134 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4556 ,  H01L2224/45599 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48453 ,  H01L2224/48465 ,  H01L2224/48507 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/48664 ,  H01L2224/48669 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48764 ,  H01L2224/48769 ,  H01L2224/48824 ,  H01L2224/48847 ,  H01L2224/48864 ,  H01L2224/49171 ,  H01L2224/78301 ,  H01L2224/85205 ,  H01L2224/85424 ,  H01L2224/85447 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/48869 ,  H01L2924/00015 ,  H01L2924/013 ,  H01L2924/00013

摘要： Methods of forming gold-aluminum electrical interconnects are described. The method may include interposing a diffusion retardant layer between the gold and the aluminum, the diffusion retardant layer including regions containing and regions substantially devoid of a diffusion retardant material; bringing into contact the diffusion retardant layer, the gold, and the aluminum; forming alloys of gold and the diffusion retardant material in regions containing the material and forming gold-aluminum intermetallic compounds in regions substantially devoid of the material; and forming a continuous electrically conducting path between the aluminum and the gold. A structure for gold-aluminum interconnect is provided. The structure may include an aluminum alloy bond pad and a diffusion retardant layer in contact with the bond pad, the diffusion retardant layer including regions containing and regions substantially devoid of a diffusion retardant material. The structure may include a gold free air ball in contact with the diffusion retardant layer.

摘要翻译： 描述形成金 - 铝电互连的方法。 该方法可以包括在金和铝之间插入扩散阻挡层，扩散阻挡层包含含有基本上没有扩散阻挡材料的区域; 与扩散阻挡层，金和铝接触; 在含有材料的区域中形成金和扩散阻挡材料的合金，并在基本上不含该材料的区域中形成金 - 铝金属间化合物; 并在铝和金之间形成连续的导电路径。 提供了金 - 铝互连结构。 该结构可以包括铝合金接合焊盘和与接合焊盘接触的扩散阻挡层，扩散阻挡层包括含有基本上没有扩散阻挡材料的区域。 该结构可以包括与扩散阻挡层接触的无金空气球。

公开(公告)号：US08105933B2

公开(公告)日：2012-01-31

申请号：US11669556

申请日：2007-01-31

申请人： Kevin J. Hess ,  Chu-Chung Lee

发明人： Kevin J. Hess ,  Chu-Chung Lee

IPC分类号： H01L21/44

CPC分类号： H01L24/85 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/1134 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4556 ,  H01L2224/45599 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48453 ,  H01L2224/48465 ,  H01L2224/48507 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/48664 ,  H01L2224/48669 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48764 ,  H01L2224/48769 ,  H01L2224/48824 ,  H01L2224/48847 ,  H01L2224/48864 ,  H01L2224/49171 ,  H01L2224/78301 ,  H01L2224/85205 ,  H01L2224/85424 ,  H01L2224/85447 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/48869 ,  H01L2924/00015 ,  H01L2924/013 ,  H01L2924/00013

摘要： In some embodiments a method of forming a gold-aluminum electrical interconnect is described. The method may include interposing a diffusion retardant layer between the gold and the aluminum (1002), the diffusion retardant layer including regions containing and regions substantially devoid of a diffusion retardant material; bringing into contact the diffusion retardant layer, the gold, and the aluminum (1004); forming alloys of gold and the diffusion retardant material in regions containing the material (1006) and forming gold-aluminum intermetallic compounds in regions substantially devoid of the material (1008); and forming a continuous electrically conducting path between the aluminum and the gold (1010). In some embodiments, a structure useful in a gold-aluminum interconnect is provided. The structure may include an aluminum alloy bond pad (530) and a diffusion retardant layer (520) in contact with the bond pad, the diffusion retardant layer including regions (522) containing and regions (524) substantially devoid of a diffusion retardant material. The structure may include a gold free air ball (714) in contact with the diffusion retardant layer.

摘要翻译： 在一些实施例中描述了形成金 - 铝电互连的方法。 该方法可以包括在金和铝之间插入扩散阻挡层（1002），扩散阻挡层包含含有基本上没有扩散阻挡材料的区域; 与扩散阻挡层，金和铝接触（1004）; 在含有材料（1006）的区域中形成金和扩散阻挡材料的合金并在基本上不含材料（1008）的区域中形成金 - 铝金属间化合物; 以及在所述铝和所述金（1010）之间形成连续的导电路径。 在一些实施例中，提供了可用于金 - 铝互连的结构。 该结构可以包括与接合焊盘接触的铝合金接合焊盘（530）和扩散阻挡层（520），所述扩散阻挡层包括含有基本上没有扩散阻挡材料的区域（522）和区域（524）。 该结构可以包括与扩散阻挡层接触的无金空气球（714）。