公开(公告)号：US09589976B2

公开(公告)日：2017-03-07

申请号：US14688201

申请日：2015-04-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yuan-Tai Tseng ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L29/788 ,  H01L29/423 ,  H01L27/12 ,  H01L27/01 ,  H01L27/115 ,  H01L21/28 ,  H01L23/48 ,  H01L29/88 ,  H01L21/306

CPC classification number: H01L27/1157 ,  H01L21/28282 ,  H01L21/30625 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/42344

Abstract: The present disclosure relates to an integrated circuit (IC), including, a flash memory device region, including a pair of split-gate flash memory cells arranged over a semiconductor substrate. The pair of split gate flash memory cells respectively have a control gate (CG) including a polysilicon gate and an overlying silicide layer. A periphery circuit including, one or more high-k metal gate (HKMG) transistors are arranged over the semiconductor substrate at a position laterally offset from the flash memory device region. The one or more HKMG transistors have a metal gate electrode with an upper surface that is lower than an upper surface of the silicide layer. A method of manufacturing the IC is also provided.

Abstract translation: 本公开涉及一种集成电路（IC），其包括闪存器件区域，其包括布置在半导体衬底上的一对分裂栅极闪存单元。 一对分裂栅极闪存单元分别具有包括多晶硅栅极和上覆硅化物层的控制栅极（CG）。 包括一个或多个高k金属栅极（HKMG）晶体管的外围电路在横向偏离闪存器件区域的位置上布置在半导体衬底的上方。 一个或多个HKMG晶体管具有金属栅电极，其上表面低于硅化物层的上表面。 还提供了一种制造IC的方法。

公开(公告)号：US09570457B2

公开(公告)日：2017-02-14

申请号：US14468410

申请日：2014-08-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chiang Min ,  Tsung-Hsueh Yang ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L27/115 ,  H01L29/792 ,  H01L29/66 ,  H01L21/28 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3105 ,  H01L29/423

CPC classification number: H01L27/11568 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/26513 ,  H01L21/28282 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/32115 ,  H01L21/32139 ,  H01L21/76897 ,  H01L29/0847 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

Abstract: A semiconductor structure for a split gate flash memory cell device with a hard mask having an asymmetric profile is provided. A semiconductor substrate of the semiconductor structure includes a first source/drain region and a second source/drain region. A control gate and a memory gate, of the semiconductor structure, are spaced over the semiconductor substrate between the first and second source/drain regions. A charge trapping dielectric structure of the semiconductor structure is arranged between neighboring sidewalls of the memory gate and the control gate, and arranged under the memory gate. A hard mask of the semiconductor structure is arranged over the control gate and includes an asymmetric profile. The asymmetric profile tapers in height away from the memory gate. A method for manufacturing a pair of split gate flash memory cell devices with hard masks having an asymmetric profile is also provided.

Abstract translation: 提供了具有非对称轮廓的硬掩模的分裂栅极闪存单元器件的半导体结构。 半导体结构的半导体衬底包括第一源极/漏极区域和第二源极/漏极区域。 半导体结构的控制栅极和存储栅极在第一和第二源极/漏极区之间的半导体衬底上间隔开。 半导体结构的电荷捕获电介质结构被布置在存储器栅极的相邻侧壁和控制栅极之间，并且布置在存储器栅极下方。 半导体结构的硬掩模布置在控制栅极上并且包括不对称轮廓。 不对称轮廓在远离记忆门的高度逐渐变细。 还提供了一种用于制造具有不对称轮廓的硬掩模的一对分裂栅极闪存单元器件的方法。

公开(公告)号：US09570454B2

公开(公告)日：2017-02-14

申请号：US14749970

申请日：2015-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming Chyi Liu ,  Chang-Ming Wu ,  Shih-Chang Liu ,  Yu-Hsing Chang ,  Yuan-Tai Tseng

IPC: H01L27/115 ,  H01L29/78 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L27/11524 ,  H01L27/11534 ,  H01L29/1037 ,  H01L29/42328 ,  H01L29/7851

Abstract: The present disclosure relates to an integrated chip having a FinFET device and an embedded flash memory device, and a method of formation. In some embodiments, the integrated chip has a logic region and a memory region that is laterally separated from the logic region. The logic region has a first plurality of fins of semiconductor material protruding outward from a semiconductor substrate. A gate electrode is arranged over the first plurality of fins of semiconductor material. The memory region has a second plurality of fins of semiconductor material extending outward from the semiconductor substrate. An embedded flash memory cell is arranged onto the second plurality of fins of semiconductor material. The resulting integrated chip structure provides for good performance since it contains both a FinFET device and an embedded flash memory device.

Abstract translation: 本公开涉及具有FinFET器件和嵌入式闪存器件的集成芯片及其形成方法。 在一些实施例中，集成芯片具有与逻辑区域横向分离的逻辑区域和存储区域。 逻辑区域具有从半导体衬底向外突出的半导体材料的第一多个翅片。 栅电极设置在半导体材料的第一多个散热片上。 存储区域具有从半导体衬底向外延伸的第二多个半导体材料翅片。 嵌入式闪存单元被布置在半导体材料的第二多个鳍上。 所得到的集成芯片结构提供了良好的性能，因为它包含FinFET器件和嵌入式闪存器件。

公开(公告)号：US20170018562A1

公开(公告)日：2017-01-19

申请号：US15277137

申请日：2016-09-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yuan-Tai Tseng ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L27/115

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/42344 ,  H01L29/518 ,  H01L29/6656 ,  H01L29/66833 ,  H01L29/792

Abstract: The present disclosure relates to a flash memory cell. In some embodiments, the flash memory cell has a control gate arranged over a substrate, and a select gate separated from the substrate by a gate dielectric layer. A charge trapping layer has a first portion disposed between the select gate and the control gate, and a second portion arranged under the control gate. A first control gate spacer is arranged on the second portion of the charge trapping layer. A second control gate spacer is arranged on the second portion of the charge trapping layer and is separated from the control gate by the first control gate spacer.

Abstract translation: 本公开涉及闪存单元。 在一些实施例中，快闪存储器单元具有布置在衬底上的控制栅极，以及通过栅极电介质层与衬底分离的选择栅极。 电荷捕获层具有设置在选择栅极和控制栅极之间的第一部分和布置在控制栅极下方的第二部分。 第一控制栅极间隔物布置在电荷俘获层的第二部分上。 第二控制栅极间隔物布置在电荷俘获层的第二部分上，并且通过第一控制栅极隔离物与控制栅极分离。

公开(公告)号：US09536888B2

公开(公告)日：2017-01-03

申请号：US14580505

申请日：2014-12-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Ming Wu ,  Harry-Hak-Lay Chuang ,  Shih-Chang Liu

IPC: H01L31/112 ,  H01L27/108 ,  H01L29/00 ,  H01L31/036 ,  H01L27/115 ,  H01L21/28

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L21/76229 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11548

Abstract: The present disclosure relates a method of forming an integrated circuit. In some embodiments, the method is performed by patterning a first masking layer over a substrate to have a first plurality of openings at a memory cell region and a second plurality of openings at a boundary region. A first plurality of dielectric bodies are formed within the first plurality of openings and a second plurality of dielectric bodies are formed within the second plurality of openings. A second masking layer is formed over the first masking layer and the first and second plurality of dielectric bodies. The first and second masking layers are removed at the memory cell region, and a first conductive layer is formed to fill recesses between the first plurality of dielectric bodies. A planarization process reduces a height of the first conductive layer and removes the first conductive layer from over the boundary region.

Abstract translation: 本公开涉及一种形成集成电路的方法。 在一些实施例中，该方法通过在衬底上图案化第一掩模层来进行，以在存储单元区域处具有第一多个开口，并在边界区域具有第二多个开口。 在所述第一多个开口内形成有第一多个介电体，并且在所述第二多个开口内形成第二多个介电体。 在第一掩蔽层和第一和第二多个电介质体之上形成第二掩模层。 在存储单元区域处去除第一和第二掩模层，并且形成第一导电层以填充第一多个电介质体之间的凹部。 平坦化处理降低了第一导电层的高度，并从边界区域上移除第一导电层。

公开(公告)号：US20160379987A1

公开(公告)日：2016-12-29

申请号：US14749970

申请日：2015-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming Chyi Liu ,  Chang-Ming Wu ,  Shih-Chang Liu ,  Yu-Hsing Chang ,  Yuan-Tai Tseng

IPC: H01L27/115 ,  H01L29/423 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L27/11524 ,  H01L27/11534 ,  H01L29/1037 ,  H01L29/42328 ,  H01L29/7851

Abstract: The present disclosure relates to an integrated chip having a FinFET device and an embedded flash memory device, and a method of formation. In some embodiments, the integrated chip has a logic region and a memory region that is laterally separated from the logic region. The logic region has a first plurality of fins of semiconductor material protruding outward from a semiconductor substrate. A gate electrode is arranged over the first plurality of fins of semiconductor material. The memory region has a second plurality of fins of semiconductor material extending outward from the semiconductor substrate. An embedded flash memory cell is arranged onto the second plurality of fins of semiconductor material. The resulting integrated chip structure provides for good performance since it contains both a FinFET device and an embedded flash memory device.

Abstract translation: 本公开涉及具有FinFET器件和嵌入式闪存器件的集成芯片及其形成方法。 在一些实施例中，集成芯片具有与逻辑区域横向分离的逻辑区域和存储区域。 逻辑区域具有从半导体衬底向外突出的半导体材料的第一多个翅片。 栅电极设置在半导体材料的第一多个散热片上。 存储区域具有从半导体衬底向外延伸的第二多个半导体材料翅片。 嵌入式闪存单元被布置在半导体材料的第二多个鳍上。 所得到的集成芯片结构提供了良好的性能，因为它包含FinFET器件和嵌入式闪存器件。

公开(公告)号：US09484351B2

公开(公告)日：2016-11-01

申请号：US14182952

申请日：2014-02-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Ming Wu ,  Wei Cheng Wu ,  Shih-Chang Liu ,  Harry-Hak-Lay Chuang ,  Chia-Shiung Tsai

IPC: H01L29/788 ,  H01L27/115 ,  H01L29/66 ,  H01L21/28 ,  H01L29/423 ,  H01L29/792

CPC classification number: H01L29/42344 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/1157 ,  H01L29/42324 ,  H01L29/42348 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792

Abstract: The present disclosure relates to a split gate memory device which requires less number of processing steps than traditional baseline processes and methods of making the same. Word gate/select gate (SG) pairs are formed around a sacrificial spacer. The resulting SG structure has a distinguishable non-planar top surface. The spacer layer that covers the select gate also follows the shape of the SG top surface. A dielectric disposed above the inter-gate dielectric layer and arranged between the neighboring sidewalls of the each memory gate and select gate provides isolation between them.

Abstract translation: 本公开涉及一种分裂门存储器件，其需要比传统的基线工艺更少数量的处理步骤及其制造方法。 字栅/选择栅极（SG）对围绕牺牲间隔物形成。 所得到的SG结构具有可区分的非平面顶表面。 覆盖选择栅的间隔层也遵循SG顶表面的形状。 设置在栅极间介电层上方并且布置在每个存储器栅极和选择栅极的相邻侧壁之间的电介质在它们之间提供隔离。

公开(公告)号：US20150279849A1

公开(公告)日：2015-10-01

申请号：US14225874

申请日：2014-03-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hsing Chang ,  Chang-Ming Wu ,  Shih-Chang Liu ,  Chia-Shiung Tsai ,  Ru-Liang Lee ,  Wei Cheng Wu ,  Harry-Hak-Lay Chuang

IPC: H01L27/115 ,  H01L21/28 ,  H01L29/788

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/11524 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7883

Abstract: Some embodiments relate to a memory cell with a charge-trapping layer of nanocrystals, comprising a tunneling oxide layer along a select gate, a control oxide layer formed between a control gate and the tunnel oxide layer, and a plurality of nanocrystals arranged between the tunneling and control oxide layers. An encapsulating layer isolates the nanocrystals from the control oxide layer. Contact formation to the select gate includes a two-step etch. A first etch includes a selectivity between oxide and the encapsulating layer, and etches away the control oxide layer while leaving the encapsulating layer intact. A second etch, which has an opposite selectivity of the first etch, then etches away the encapsulating layer while leaving the tunneling oxide layer intact. As a result, the control oxide layer and nanocrystals are etched away from a surface of the select gate, while leaving the tunneling oxide layer intact for contact isolation.

Abstract translation: 一些实施例涉及具有纳米晶体的电荷捕获层的存储器单元，其包括沿着选择栅极的隧穿氧化物层，形成在控制栅极和隧道氧化物层之间的控制氧化物层，以及多个纳米晶体，其布置在隧道 并控制氧化物层。 封装层将纳米晶体与控制氧化物层隔离。 与选择栅极的接触形成包括两步蚀刻。 第一蚀刻包括氧化物和封装层之间的选择性，并且蚀刻掉控制氧化物层，同时保持封装层完好无损。 具有与第一蚀刻相反的选择性的第二蚀刻然后在完全留下隧道氧化物层的同时蚀刻封装层。 结果，将控制氧化物层和纳米晶体从选择栅极的表面蚀刻掉，同时使隧道氧化物层完好无损以进行接触隔离。

公开(公告)号：US10962878B2

公开(公告)日：2021-03-30

申请号：US16666679

申请日：2019-10-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ping-Yin Liu ,  Chang-Ming Wu ,  Chia-Shiung Tsai ,  Xin-Hua Huang

IPC: G03F7/20 ,  G03F1/64 ,  G03F1/62

Abstract: A method for forming a pellicle apparatus involves forming a device substrate by depositing one or more pellicle layers defined over a base device layer, where a release layer is formed thereover. An adhesive layer is formed over a transparent carrier substrate. The adhesive layer is bonded to the release layer, defining a composite substrate comprised of the device and carrier substrates. The base device layer is removed from the composite structure and a pellicle frame is attached to an outermost one of the pellicle layers. A pellicle region is isolated from a remainder of the composite structure, and an ablation of the release layer is performed through the transparent carrier substrate, defining the pellicle apparatus comprising a pellicle film attached to the pellicle frame. The pellicle apparatus is then from a remaining portion of the composite substrate.

公开(公告)号：US10276584B2

公开(公告)日：2019-04-30

申请号：US15408994

申请日：2017-01-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chiang Min ,  Tsung-Hsueh Yang ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L21/28 ,  H01L29/08 ,  H01L29/66 ,  H01L21/033 ,  H01L21/265 ,  H01L21/311 ,  H01L21/321 ,  H01L21/768 ,  H01L29/423 ,  H01L29/792 ,  H01L21/3105 ,  H01L21/3213 ,  H01L27/11568

Abstract: A semiconductor structure for a split gate flash memory cell device with a hard mask having an asymmetric profile is provided. In some embodiments, a semiconductor substrate of the semiconductor structure includes a first source/drain region and a second source/drain region. A control gate and a memory gate, of the semiconductor structure, are spaced over the semiconductor substrate between the first and second source/drain regions. A charge trapping dielectric structure of the semiconductor structure is arranged between neighboring sidewalls of the memory gate and the control gate, and arranged under the memory gate. A hard mask of the semiconductor structure is arranged over the control gate and includes an asymmetric profile. The asymmetric profile tapers in height away from the memory gate. A method for manufacturing a pair of split gate flash memory cell devices with hard masks having an asymmetric profile is also provided.