公开(公告)号：US08994176B2

公开(公告)日：2015-03-31

申请号：US13713034

申请日：2012-12-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kai-Chiang Wu ,  Hsien-Wei Chen ,  Yu-Feng Chen ,  Chun-Hung Lin ,  Ming-Kai Liu ,  Chun-Lin Lu

IPC: H01L23/48 ,  H01L23/498 ,  H01L21/56 ,  H01L25/10 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/52 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/5386 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05572 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1144 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1712 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1443 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H05K1/0284 ,  H05K1/0313 ,  H05K1/111 ,  H05K1/181 ,  H05K3/40 ,  H05K2201/09409 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Methods and apparatus for an interposer with dams used in packaging dies are disclosed. An interposer may comprise a metal layer above a substrate. A plurality of dams may be formed above the metal layer around each corner of the metal layer. Dams may be formed on both sides of the interposer substrate. A dam surrounds an area where connectors such as solder balls may be located to connect to other packages. A non-conductive dam may be formed above the dam. An underfill may be formed under the package connected to the connector, above the metal layer, and contained within the area surrounded by the dams at the corner, so that the connectors are well protected by the underfill. Such dams may be further formed on a printed circuit board as well.

Abstract translation: 公开了用于包装模具中使用的用于插座的插入件的方法和装置。 插入件可以包括衬底上方的金属层。 可以在金属层的金属层的每个角落周围形成多个堤坝。 可以在插入器基板的两侧上形成大坝。 大坝围绕可能位于连接器如焊球的区域以连接到其他包装。 坝上可能形成非导电坝。 可以在金属层上方连接到连接器的封装下方形成底部填充物，并且包含在由角落处的堤坝包围的区域内，使得连接器被底部填充物良好地保护。 这样的堤坝也可以进一步形成在印刷电路板上。

公开(公告)号：US20140167263A1

公开(公告)日：2014-06-19

申请号：US13713034

申请日：2012-12-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Kai-Chiang Wu ,  Hsien-Wei Chen ,  Yu-Feng Chen ,  Chun-Hung Lin ,  Ming-Kai Liu ,  Chun-Lin Lu

IPC: H01L23/00 ,  H01L21/50

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/52 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/5386 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05572 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1144 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1712 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1443 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H05K1/0284 ,  H05K1/0313 ,  H05K1/111 ,  H05K1/181 ,  H05K3/40 ,  H05K2201/09409 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Methods and apparatus for an interposer with dams used in packaging dies are disclosed. An interposer may comprise a metal layer above a substrate. A plurality of dams may be formed above the metal layer around each corner of the metal layer. Dams may be formed on both sides of the interposer substrate. A dam surrounds an area where connectors such as solder balls may be located to connect to other packages. A non-conductive dam may be formed above the dam. An underfill may be formed under the package connected to the connector, above the metal layer, and contained within the area surrounded by the dams at the corner, so that the connectors are well protected by the underfill. Such dams may be further formed on a printed circuit board as well.

Abstract translation: 公开了用于包装模具中使用的用于插座的插入件的方法和装置。 插入件可以包括衬底上方的金属层。 可以在金属层的金属层的每个角落周围形成多个堤坝。 可以在插入器基板的两侧上形成大坝。 大坝围绕可能位于连接器如焊球的区域以连接到其他包装。 坝上可能形成非导电坝。 可以在金属层上方连接到连接器的封装下方形成底部填充物，并且包含在由角落处的堤坝包围的区域内，使得连接器被底部填充物良好地保护。 这样的堤坝也可以进一步形成在印刷电路板上。

公开(公告)号：US10691017B2

公开(公告)日：2020-06-23

申请号：US16181637

申请日：2018-11-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Ching Lee ,  Ching-Fang Yu ,  Chun-Hung Lin ,  Ting-Hao Hsu ,  Ching-Hsiang Chang ,  Sheng-Chi Chin

IPC: G03F1/64 ,  G03F7/20

Abstract: Pellicle-mask systems for advanced lithography, such as extreme ultraviolet lithography, are disclosed herein. An exemplary pellicle-mask system includes a mask having an integrated circuit (IC) pattern, a pellicle membrane, and a pellicle frame. The pellicle frame has a first surface attached to the pellicle membrane and a second surface opposite the first surface attached to the mask, such that the IC pattern of the mask is positioned within an enclosed space defined by the mask, the pellicle membrane, and the pellicle frame. A void is defined between the pellicle frame and the mask, where the void is defined by a portion of the second surface of the pellicle membrane not attached to the mask. The void is not in communication with the enclosed space and is not in communication with an exterior space of the pellicle-mask system.

公开(公告)号：US10163734B2

公开(公告)日：2018-12-25

申请号：US15648032

申请日：2017-07-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chen-Hua Yu ,  Chih-Fan Huang ,  Chun-Hung Lin ,  Ming-Da Cheng ,  Chung-Shi Liu ,  Mirng-Ji Lii

IPC: H01L21/66 ,  H01L21/56 ,  H01L21/268 ,  H01L25/00 ,  H01L23/00 ,  H01L29/78 ,  H01L23/31

Abstract: A method includes followings operations. A substrate including a first surface and a second surface is provided. The substrate and a transparent film are heated to attach the transparent film on the first surface. A first coefficient of a thermal expansion (CTE) mismatch is between the substrate and the transparent film. The substrate and the transparent film are cooled. A polymeric material is disposed on the second surface. A second CTE mismatch is between the substrate and the polymeric material. The second CTE mismatch is counteracted by the first CTE mismatch.

公开(公告)号：US10020276B2

公开(公告)日：2018-07-10

申请号：US15346493

申请日：2016-11-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Shien Chen ,  Yu-Feng Chen ,  Yu-Wei Lin ,  Tin-Hao Kuo ,  Yu-Min Liang ,  Chun-Hung Lin

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L24/16 ,  H01L21/481 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/13 ,  H01L2224/13016 ,  H01L2224/13082 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/81

Abstract: An embodiment apparatus includes a dielectric layer in a die, a conductive trace in the dielectric layer, and a protrusion bump pad on the conductive trace. The protrusion bump pad at least partially extends over the dielectric layer, and the protrusion bump pad includes a lengthwise axis and a widthwise axis. A ratio of a first dimension of the lengthwise axis to a second dimension of the widthwise axis is about 0.8 to about 1.2.

公开(公告)号：US09933699B2

公开(公告)日：2018-04-03

申请号：US14658399

申请日：2015-03-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yu-Ching Lee ,  Ching-Fang Yu ,  Chun-Hung Lin ,  Sheng-Chi Chin ,  Ting-Hao Hsu ,  Mark Chang

IPC: G01H1/00 ,  G01H9/00 ,  G01H13/00 ,  G01L1/00 ,  G01M7/00 ,  G01N3/32 ,  G01N21/00 ,  G01N24/00 ,  G01N29/00 ,  G01N29/04 ,  G03F1/84 ,  G03F1/62

CPC classification number: G03F1/84 ,  G03F1/62

Abstract: A pellicle is disposed over a lithography mask. An acoustic wave generator is placed over the pellicle. The acoustic wave generator is configured to generate acoustic waves to cause the pellicle to vibrate at a target resonance frequency. A resonance detection tool is configured to detect an actual resonance frequency of the pellicle in response to the acoustic waves. One or more electronic processors are configured to estimate an age condition of the pellicle as a function of a shift of the actual resonance frequency from the target resonance frequency.

公开(公告)号：US20170227843A1

公开(公告)日：2017-08-10

申请号：US15019478

申请日：2016-02-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Ching Lee ,  Ching-Fang Yu ,  Chun-Hung Lin ,  Ting-Hao Hsu ,  Ching-Hsiang Chang ,  Sheng-Chi Chin

IPC: G03F1/64 ,  G03F7/20

CPC classification number: G03F1/64 ,  G03F7/2004

Abstract: The present disclosure provides an apparatus for a semiconductor lithography process in accordance with some embodiments. The apparatus includes a pellicle membrane, a pellicle frame attached to the pellicle membrane. The pellicle frame has a surface that defines at least one groove. The apparatus further includes a substrate that is in contact with the surface of the pellicle frame such that the grove is positioned between the pellicle frame and the substrate.

公开(公告)号：US09728427B2

公开(公告)日：2017-08-08

申请号：US15077237

申请日：2016-03-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chen-Hua Yu ,  Chih-Fan Huang ,  Chun-Hung Lin ,  Ming-Da Cheng ,  Chung-Shi Liu ,  Mirng-Ji Lii

IPC: H01L21/56 ,  H01L29/78 ,  H01L25/00 ,  H01L23/00 ,  H01L21/66 ,  H01L21/268 ,  H01L23/31

CPC classification number: H01L22/12 ,  H01L21/268 ,  H01L21/561 ,  H01L21/566 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/562 ,  H01L24/83 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L29/7847 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/83192 ,  H01L2224/83868 ,  H01L2224/83871 ,  H01L2224/97 ,  H01L2924/0002 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2924/00014

Abstract: A method includes followings operations. A substrate including a first surface and a second surface is provided. The substrate and a transparent film are heated to attach the transparent film on the first surface. A first coefficient of a thermal expansion (CTE) mismatch is between the substrate and the transparent film. The substrate and the transparent film are cooled. A polymeric material is disposed on the second surface. A second CTE mismatch is between the substrate and the polymeric material. The second CTE mismatch is counteracted by the first CTE mismatch.

公开(公告)号：US20170025394A1

公开(公告)日：2017-01-26

申请号：US15289681

申请日：2016-10-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Hung Lin

IPC: H01L25/065 ,  H01L21/78 ,  H01L23/00 ,  H01L21/56

Abstract: A chip includes a semiconductor substrate, an electrical connector over the semiconductor substrate, and a molding compound molding a lower part of the electrical connector therein. A top surface of the molding compound is lower than a top end of the electrical connector. A recess extends from the top surface of the molding compound into the molding compound.

Abstract translation: 芯片包括半导体衬底，半导体衬底上的电连接器，以及将电连接器的下部模制成型的模制复合体。 模制化合物的顶表面低于电连接器的顶端。 凹部从模塑料的顶表面延伸到模塑料中。

公开(公告)号：US09508637B2

公开(公告)日：2016-11-29

申请号：US14456812

申请日：2014-08-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Shien Chen ,  Yu-Feng Chen ,  Yu-Wei Lin ,  Tin-Hao Kuo ,  Yu-Min Liang ,  Chun-Hung Lin

IPC: H01L21/00 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L24/16 ,  H01L21/481 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/13 ,  H01L2224/13016 ,  H01L2224/13082 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/81

Abstract: An embodiment apparatus includes a dielectric layer in a die, a conductive trace in the dielectric layer, and a protrusion bump pad on the conductive trace. The protrusion bump pad at least partially extends over the dielectric layer, and the protrusion bump pad includes a lengthwise axis and a widthwise axis. A ratio of a first dimension of the lengthwise axis to a second dimension of the widthwise axis is about 0.8 to about 1.2.

Abstract translation: 一种实施方式的装置包括：管芯中的电介质层，电介质层中的导电迹线，以及导电迹线上的突起焊盘。 突起凸块至少部分地延伸在电介质层上，并且突起凸块垫包括纵向轴线和宽度方向轴线。 纵向轴线的第一尺寸与宽度方向轴线的第二尺寸的比率为约0.8至约1.2。