公开(公告)号：US08723574B2

公开(公告)日：2014-05-13

申请号：US13363832

申请日：2012-02-01

申请人： Yoshihiro Tomita

发明人： Yoshihiro Tomita

IPC分类号： H03K3/289

CPC分类号： H03K3/356156 ,  H01L27/0207 ,  H01L27/092

摘要： According to one embodiment, a semiconductor integrated circuit is provided, which has mounted thereto a flip-flop circuit including a latch portion that takes and holds input data based upon a clock signal, and a clock portion that inputs the clock signal to the latch portion, wherein an active region of the flip-flop circuit is divided in such a manner that the width of the active region is secured, and each of the active regions has uniform width.

摘要翻译： 根据一个实施例，提供一种半导体集成电路，其已经安装有包括基于时钟信号取入并保持输入数据的锁存部分的触发器电路和将时钟信号输入到锁存部分的时钟部分 其中触发器电路的有源区域以确保有源区域的宽度的方式被划分，并且每个有源区域具有均匀的宽度。

公开(公告)号：US08669648B2

公开(公告)日：2014-03-11

申请号：US13414086

申请日：2012-03-07

申请人： Yoshihiro Tomita

发明人： Yoshihiro Tomita

IPC分类号： H01L23/495

CPC分类号： H01L25/16 ,  H01L23/142 ,  H01L23/36 ,  H01L23/49562 ,  H01L23/49575 ,  H01L2224/48137 ,  H01L2224/4903 ,  H01L2224/49171 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/3025 ,  H01L2924/00

摘要： A driver IC which is operated by a power supply system insulated from a control IC is mounted in the vicinity of a switching element on a first conductor pattern. A second conductor pattern connected to a source terminal or an emitter terminal of the switching element is electrically connected to a third conductor pattern on which the driver IC is mounted. A ground terminal of the driver IC is electrically connected to the third conductor pattern, and a drive terminal of the driver IC is electrically connected to a gate terminal or a base terminal of the switching element.

摘要翻译： 由与控制IC绝缘的电源系统操作的驱动器IC安装在第一导体图案上的开关元件附近。 连接到开关元件的源极端子或发射极端子的第二导体图案电连接到其上安装有驱动器IC的第三导体图案。 驱动器IC的接地端子电连接到第三导体图案，驱动器IC的驱动端子电连接到开关元件的栅极端子或基极端子。

公开(公告)号：US20130292838A1

公开(公告)日：2013-11-07

申请号：US13939146

申请日：2013-07-10

申请人： Sanka Ganesan ,  Yosuke Kanaoka ,  Ram S. Viswanath ,  Rajasekaran Swaminathan ,  Robert M. Nickerson ,  Leonel R. Arana ,  John S. Guzek ,  Yoshihiro Tomita

发明人： Sanka Ganesan ,  Yosuke Kanaoka ,  Ram S. Viswanath ,  Rajasekaran Swaminathan ,  Robert M. Nickerson ,  Leonel R. Arana ,  John S. Guzek ,  Yoshihiro Tomita

IPC分类号： H01L23/488 ,  H01L21/50

CPC分类号： H01L23/488 ,  H01L21/50 ,  H01L23/3128 ,  H01L23/49833 ,  H01L23/562 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Embodiments of the invention relate to a package-on-package (PoP) assembly comprising a top device package and a bottom device package interconnected by way of an electrically interconnected planar stiffener. Embodiments of the invention include a first semiconductor package having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads; a second semiconductor package having a plurality of SLI pads on the bottom side of the package; and a planar stiffener having a first plurality of planar contact pads on the top side of the stiffener electrically connected to the SLI pads of the second package, and a second plurality of planar contact pads electrically connected to the inter-package contact pads of the first package.

摘要翻译： 本发明的实施例涉及一种封装封装（PoP）组件，其包括顶部器件封装和通过电互连平面加强件互连的底部器件封装。 本发明的实施例包括具有多个封装间接触焊盘和多个第二级互连（SLI）焊盘的第一半导体封装; 第二半导体封装，其具有在封装的底侧上的多个SLI焊盘; 以及平面加强件，其具有电连接到所述第二封装的SLI焊盘的所述加强件的顶侧上的第一多个平面接触焊盘，以及电连接到所述第一封装的所述封装间接触焊盘的第二多个平面接触焊盘 包。

公开(公告)号：US08513792B2

公开(公告)日：2013-08-20

申请号：US12384984

申请日：2009-04-10

申请人： Sanka Ganesan ,  Yosuke Kanaoka ,  Ram S. Viswanath ,  Rajasekaran Swaminathan ,  Robert M. Nickerson ,  Leonel R. Arana ,  John S. Guzek ,  Yoshihiro Tomita

发明人： Sanka Ganesan ,  Yosuke Kanaoka ,  Ram S. Viswanath ,  Rajasekaran Swaminathan ,  Robert M. Nickerson ,  Leonel R. Arana ,  John S. Guzek ,  Yoshihiro Tomita

IPC分类号： H01L23/02 ,  H01L23/34 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/488 ,  H01L21/50 ,  H01L23/3128 ,  H01L23/49833 ,  H01L23/562 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Embodiments of the invention relate to a package-on-package (PoP) assembly comprising a top device package and a bottom device package interconnected by way of an electrically interconnected planar stiffener. Embodiments of the invention include a first semiconductor package having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads; a second semiconductor package having a plurality of SLI pads on the bottom side of the package; and a planar stiffener having a first plurality of planar contact pads on the top side of the stiffener electrically connected to the SLI pads of the second package, and a second plurality of planar contact pads electrically connected to the inter-package contact pads of the first package.

摘要翻译： 本发明的实施例涉及一种封装封装（PoP）组件，其包括顶部器件封装和通过电互连平面加强件互连的底部器件封装。 本发明的实施例包括具有多个封装间接触焊盘和多个第二级互连（SLI）焊盘的第一半导体封装; 第二半导体封装，其具有在封装的底侧上的多个SLI焊盘; 以及平面加强件，其具有电连接到所述第二封装的SLI焊盘的所述加强件的顶侧上的第一多个平面接触焊盘，以及电连接到所述第一封装的所述封装间接触焊盘的第二多个平面接触焊盘 包。

公开(公告)号：US08227907B2

公开(公告)日：2012-07-24

申请号：US13004815

申请日：2011-01-11

申请人： Yoshihiro Tomita ,  David Chau ,  Gregory M. Chrysler ,  Devendra Natekar

发明人： Yoshihiro Tomita ,  David Chau ,  Gregory M. Chrysler ,  Devendra Natekar

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L21/4867 ,  H01L21/563 ,  H01L23/3675 ,  H01L23/42 ,  H01L23/5389 ,  H01L24/24 ,  H01L2223/6677 ,  H01L2224/16225 ,  H01L2224/18 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/351 ,  H01L2924/00

摘要： An embodiment of the present invention is a technique to fabricate a metal interconnect. A first metal trace is printed on a die attached to a substrate or a cavity of a heat spreader in a package to electrically connect the first metal trace to a power contact in the substrate. A device is mounted on the first metal trace. The device receives power from the substrate when the package is powered.

摘要翻译： 本发明的一个实施例是制造金属互连的技术。 将第一金属迹线印刷在附接到封装中的散热器的基板或空腔的管芯上，以将第一金属迹线电连接到基板中的电源触点。 设备安装在第一个金属轨迹上。 当封装电源时，该设备从基板接收电力。

公开(公告)号：US07973412B2

公开(公告)日：2011-07-05

申请号：US12342347

申请日：2008-12-23

申请人： Seiji Fujiwara ,  Yoshihiro Tomita ,  Akio Furusawa ,  Kenichirou Suetugu

发明人： Seiji Fujiwara ,  Yoshihiro Tomita ,  Akio Furusawa ,  Kenichirou Suetugu

IPC分类号： H01L23/48 ,  H01L21/52 ,  C22C12/00 ,  B23K35/26

CPC分类号： C22C12/00 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/04042 ,  H01L2224/0603 ,  H01L2224/29 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/29113 ,  H01L2224/29298 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83455 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/0133 ,  H01L2924/0134 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01028 ,  H01L2924/01083 ,  H01L2924/3512 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929

摘要： In a semiconductor device bonded to a motherboard with a bonding material having a melting point of 200° C. to 230° C., a bonding material 15 which is a die bonding material for bonding a semiconductor element 13 to a semiconductor substrate 11 is a Bi alloy containing 0.8 wt % to 10 wt % of Cu and 0.02 wt % to 0.2 wt % of Ge, so that the bonding material 15 for bonding the semiconductor element 13 to the semiconductor substrate 11 is not melted when the semiconductor device is bonded to the motherboard by reflowing. It is therefore possible to suppress poor connection on the semiconductor element 13, thereby securing the mountability and electrical reliability of the semiconductor device.

摘要翻译： 在用熔点为200℃〜230℃的接合材料接合到母板的半导体器件中，作为用于将半导体元件13接合到半导体基板11的芯片接合材料的接合材料15是 含有0.8重量％〜10重量％的Cu和0.02重量％〜0.2重量％的Ge的Bi合金，使得当将半导体元件13接合到半导体基板11时，用于将半导体元件13接合到半导体基板11的接合材料15不熔化 主板通过回流。 因此，可以抑制半导体元件13的不良连接，从而确保半导体器件的安装性和电可靠性。

公开(公告)号：US07915697B2

公开(公告)日：2011-03-29

申请号：US12404923

申请日：2009-03-16

申请人： Masanori Minamio ,  Yoshihiro Tomita

发明人： Masanori Minamio ,  Yoshihiro Tomita

IPC分类号： G01L9/00

CPC分类号： H01L21/67248 ,  H01L21/67063

摘要： The sensor device includes: a converter body made of silicon in the shape of a rhombus in plan, the converter body having an opening in the shape of a hexagon in plan; a substrate for holding the converter body; a movable film formed on the opening; a converter electrode formed on the converter body; and a substrate electrode formed on the substrate, the substrate electrode being electrically connected with the converter electrode. The opening is placed so that four of the six sides of the hexagon extend along the four sides of the rhombus of the converter body.

摘要翻译： 该传感器装置包括：平面内呈菱形形状的硅转换体，该转换体具有平面形状的六边形开口; 用于保持转换器主体的基板; 形成在开口上的可动膜; 形成在所述转换器主体上的转换器电极; 以及形成在所述基板上的基板电极，所述基板电极与所述转换器电极电连接。 放置开口使得六边形的六个边中的四个沿着转换器主体的菱形的四边延伸。

公开(公告)号：US07882628B2

公开(公告)日：2011-02-08

申请号：US11755733

申请日：2007-05-30

申请人： Sriram Muthukumar ,  Raul Mancera ,  Yoshihiro Tomita ,  Chi-won Hwang

发明人： Sriram Muthukumar ,  Raul Mancera ,  Yoshihiro Tomita ,  Chi-won Hwang

IPC分类号： H01K3/10

CPC分类号： H01L23/147 ,  H01L23/481 ,  H01L23/49827 ,  H01L25/0655 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/16225 ,  H01L2924/10253 ,  H01L2924/15311 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49165 ,  Y10T29/49169 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013 ,  H01L2924/04941

摘要： The formation of electronic assemblies is described. One embodiment includes providing a body and forming a first metal pad layer on a first surface thereof. A second metal pad layer is formed in contact with the first metal pad layer, the second metal pad layer having a denser pitch than the first metal pad layer. A dielectric layer is formed between the metal pads in the first and second metal pad layers. Vias extending through the body from a second surface thereof are formed, the vias exposing the first metal pad layer. An insulating layer is formed on via sidewalls and on the second surface, and an electrically conductive layer formed on the insulating layer and on the exposed surface of the first metal layer. Elements are coupled to the second metal pad layer and the electrically conductive layer coupled to a substrate. Other embodiments are described and claimed.

摘要翻译： 描述了电子组件的形成。 一个实施例包括提供主体并在其第一表面上形成第一金属垫层。 形成与第一金属焊盘层接触的第二金属焊盘层，第二金属焊盘层的间距比第一金属焊盘层更致密。 在第一和第二金属焊盘层中的金属焊盘之间形成电介质层。 形成从其第二表面延伸穿过本体的通孔，露出第一金属垫层的通孔。 在通孔侧壁和第二表面上形成绝缘层，以及形成在第一金属层的绝缘层和暴露表面上的导电层。 元件耦合到第二金属焊盘层和耦合到衬底的导电层。 描述和要求保护其他实施例。

公开(公告)号：US07868336B2

公开(公告)日：2011-01-11

申请号：US12264539

申请日：2008-11-04

申请人： Hiroaki Fujimoto ,  Yoshihiro Tomita

发明人： Hiroaki Fujimoto ,  Yoshihiro Tomita

IPC分类号： H01L33/00 ,  H01L23/02 ,  H01L21/00

CPC分类号： H01L27/14618 ,  H01L24/94 ,  H01L27/14636 ,  H01L27/14683 ,  H01L2224/73204

摘要： According to the present invention, protrusions 4 are formed on electrodes 3 of semiconductor elements 6, and an optical member 7 is secured on the semiconductor element 6 with an adhesive 8 so as to be pressed onto the protrusions 4.

摘要翻译： 根据本发明，在半导体元件6的电极3上形成突起4，用粘合剂8将光学部件7固定在半导体元件6上，从而被压在突起4上。

公开(公告)号：US20090238394A1

公开(公告)日：2009-09-24

申请号：US12396010

申请日：2009-03-02

申请人： Masanori Minamio ,  Yoshihiro Tomita ,  Koji Nomura

发明人： Masanori Minamio ,  Yoshihiro Tomita ,  Koji Nomura

IPC分类号： H04R1/00 ,  H04R31/00

CPC分类号： H04R31/00 ,  Y10T29/49005

摘要： A microphone includes: a substrate including a tone hole and having a top surface on which a substrate electrode is provided; a converter provided on the top surface of the substrate and including a main body having a back space, a diaphragm provided at the bottom of the back space of the main body, and a converter electrode provided on a region of a bottom surface of the main body facing the substrate electrode; and a bump connecting the substrate electrode and the converter electrode to each other. The diaphragm vibrates in response to sound entering from the tone hole. The converter converts sound into a signal.

摘要翻译： 麦克风包括：包括音孔并具有其上设置有基板电极的顶表面的基板; 设置在所述基板的上表面上的转换器，具有设置在所述主体的后部空间的底部的隔膜，设置在所述主体的后部空间的底部的隔膜以及设置在所述主体的底面的区域的转换电极 身体面向衬底电极; 以及将基板电极和转换器电极彼此连接的凸块。 响应于从音孔进入的声音，隔膜振动。 转换器将声音转换为信号。