公开(公告)号：US20130292838A1

公开(公告)日：2013-11-07

申请号：US13939146

申请日：2013-07-10

申请人： Sanka Ganesan ,  Yosuke Kanaoka ,  Ram S. Viswanath ,  Rajasekaran Swaminathan ,  Robert M. Nickerson ,  Leonel R. Arana ,  John S. Guzek ,  Yoshihiro Tomita

发明人： Sanka Ganesan ,  Yosuke Kanaoka ,  Ram S. Viswanath ,  Rajasekaran Swaminathan ,  Robert M. Nickerson ,  Leonel R. Arana ,  John S. Guzek ,  Yoshihiro Tomita

IPC分类号： H01L23/488 ,  H01L21/50

CPC分类号： H01L23/488 ,  H01L21/50 ,  H01L23/3128 ,  H01L23/49833 ,  H01L23/562 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Embodiments of the invention relate to a package-on-package (PoP) assembly comprising a top device package and a bottom device package interconnected by way of an electrically interconnected planar stiffener. Embodiments of the invention include a first semiconductor package having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads; a second semiconductor package having a plurality of SLI pads on the bottom side of the package; and a planar stiffener having a first plurality of planar contact pads on the top side of the stiffener electrically connected to the SLI pads of the second package, and a second plurality of planar contact pads electrically connected to the inter-package contact pads of the first package.

摘要翻译： 本发明的实施例涉及一种封装封装（PoP）组件，其包括顶部器件封装和通过电互连平面加强件互连的底部器件封装。 本发明的实施例包括具有多个封装间接触焊盘和多个第二级互连（SLI）焊盘的第一半导体封装; 第二半导体封装，其具有在封装的底侧上的多个SLI焊盘; 以及平面加强件，其具有电连接到所述第二封装的SLI焊盘的所述加强件的顶侧上的第一多个平面接触焊盘，以及电连接到所述第一封装的所述封装间接触焊盘的第二多个平面接触焊盘 包。

公开(公告)号：US08513792B2

公开(公告)日：2013-08-20

申请号：US12384984

申请日：2009-04-10

申请人： Sanka Ganesan ,  Yosuke Kanaoka ,  Ram S. Viswanath ,  Rajasekaran Swaminathan ,  Robert M. Nickerson ,  Leonel R. Arana ,  John S. Guzek ,  Yoshihiro Tomita

发明人： Sanka Ganesan ,  Yosuke Kanaoka ,  Ram S. Viswanath ,  Rajasekaran Swaminathan ,  Robert M. Nickerson ,  Leonel R. Arana ,  John S. Guzek ,  Yoshihiro Tomita

IPC分类号： H01L23/02 ,  H01L23/34 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/488 ,  H01L21/50 ,  H01L23/3128 ,  H01L23/49833 ,  H01L23/562 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Embodiments of the invention relate to a package-on-package (PoP) assembly comprising a top device package and a bottom device package interconnected by way of an electrically interconnected planar stiffener. Embodiments of the invention include a first semiconductor package having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads; a second semiconductor package having a plurality of SLI pads on the bottom side of the package; and a planar stiffener having a first plurality of planar contact pads on the top side of the stiffener electrically connected to the SLI pads of the second package, and a second plurality of planar contact pads electrically connected to the inter-package contact pads of the first package.

摘要翻译： 本发明的实施例涉及一种封装封装（PoP）组件，其包括顶部器件封装和通过电互连平面加强件互连的底部器件封装。 本发明的实施例包括具有多个封装间接触焊盘和多个第二级互连（SLI）焊盘的第一半导体封装; 第二半导体封装，其具有在封装的底侧上的多个SLI焊盘; 以及平面加强件，其具有电连接到所述第二封装的SLI焊盘的所述加强件的顶侧上的第一多个平面接触焊盘，以及电连接到所述第一封装的所述封装间接触焊盘的第二多个平面接触焊盘 包。

公开(公告)号：US20100258927A1

公开(公告)日：2010-10-14

申请号：US12384984

申请日：2009-04-10

申请人： Sanka Ganesan ,  Yosuke Kanaoka ,  Ram S. Viswanath ,  Rajasekaran Swaminathan ,  Robert M. Nickerson ,  Leonel R. Arane ,  John S. Guzek ,  Yoshihiro Tomita

发明人： Sanka Ganesan ,  Yosuke Kanaoka ,  Ram S. Viswanath ,  Rajasekaran Swaminathan ,  Robert M. Nickerson ,  Leonel R. Arane ,  John S. Guzek ,  Yoshihiro Tomita

IPC分类号： H01L23/488 ,  H01L21/60

CPC分类号： H01L23/488 ,  H01L21/50 ,  H01L23/3128 ,  H01L23/49833 ,  H01L23/562 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Embodiments of the invention relate to a package-on-package (PoP) assembly comprising a top device package and a bottom device package interconnected by way of an electrically interconnected planar stiffener. Embodiments of the invention include a first semiconductor package having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads; a second semiconductor package having a plurality of SLI pads on the bottom side of the package; and a planar stiffener having a first plurality of planar contact pads on the top side of the stiffener electrically connected to the SLI pads of the second package, and a second plurality of planar contact pads electrically connected to the inter-package contact pads of the first package.

摘要翻译： 本发明的实施例涉及一种封装封装（PoP）组件，其包括顶部器件封装和通过电互连平面加强件互连的底部器件封装。 本发明的实施例包括具有多个封装间接触焊盘和多个第二级互连（SLI）焊盘的第一半导体封装; 第二半导体封装，其具有在封装的底侧上的多个SLI焊盘; 以及平面加强件，其具有与所述第二封装的SLI焊盘电连接的所述加强件的顶侧上的第一多个平面接触焊盘，以及电连接到所述第一封装的所述封装间接触焊盘的第二多个平面接触焊盘 包。

公开(公告)号：US20150118870A1

公开(公告)日：2015-04-30

申请号：US14065281

申请日：2013-10-28

申请人： Rajasekaran Swaminathan ,  Ram S. Viswanath ,  Sanka Ganesan ,  Gaurav Chawla ,  Joshua D. Heppner ,  Jeffory L. Smalley ,  Vijaykumar Krithivasan ,  David J. Llapitan ,  Neal E. Ulen ,  Donald T. Tran

发明人： Rajasekaran Swaminathan ,  Ram S. Viswanath ,  Sanka Ganesan ,  Gaurav Chawla ,  Joshua D. Heppner ,  Jeffory L. Smalley ,  Vijaykumar Krithivasan ,  David J. Llapitan ,  Neal E. Ulen ,  Donald T. Tran

IPC分类号： H01R12/71 ,  H01R43/00

CPC分类号： H05K7/10 ,  H01R12/00 ,  H01R12/716 ,  H01R13/2442 ,  H05K1/00 ,  Y10T29/49169

摘要： Embodiments related to integrated circuit (IC) connectors are described. In some embodiments, an IC assembly may include an IC package substrate, an intermediate member, and a male connector. The IC package substrate may have first signal contacts on a top or bottom surface, and the bottom surface may have second signal contacts for coupling with a socket on a circuit board. The intermediate member may have a first end coupled to the first signal contacts and a second end extending beyond the side surface. The male connector may be disposed at the second end of the intermediate member, and may have signal contacts coupled to the signal contacts of the intermediate member. The male connector may be mateable with a female connector when the female connector is brought into engagement in a direction parallel to the axis of the intermediate member. Other embodiments may be disclosed and/or claimed.

摘要翻译： 描述了与集成电路（IC）连接器相关的实施例。 在一些实施例中，IC组件可以包括IC封装衬底，中间构件和阳连接器。 IC封装基板可以在顶表面或底表面上具有第一信号触点，并且底表面可以具有用于与电路板上的插座耦合的第二信号触点。 中间构件可以具有联接到第一信号触头的第一端和延伸超过侧表面的第二端。 阳连接器可以设置在中间构件的第二端处，并且可以具有联接到中间构件的信号触点的信号触点。 当阴连接器沿平行于中间构件的轴线的方向接合时，阳连接器可与母连接器配合。 可以公开和/或要求保护其他实施例。

公开(公告)号：US20160183374A1

公开(公告)日：2016-06-23

申请号：US14575775

申请日：2014-12-18

申请人： Mani Prakash ,  Thomas T. Holden ,  Jeffory L. Smalley ,  Ram S. Viswanath ,  Bassam N. Coury ,  Dimitrios Ziakas ,  Chong J. Zhao ,  Jonathan W. Thibado ,  Gregorio R. Murtagian ,  Kuang C. Liu ,  Rajasekaran Swaminathan ,  Zhichao Zhang ,  John M. Lynch ,  David J. Llapitan ,  Sanka Ganesan ,  Xiang Li ,  George Vergis

发明人： Mani Prakash ,  Thomas T. Holden ,  Jeffory L. Smalley ,  Ram S. Viswanath ,  Bassam N. Coury ,  Dimitrios Ziakas ,  Chong J. Zhao ,  Jonathan W. Thibado ,  Gregorio R. Murtagian ,  Kuang C. Liu ,  Rajasekaran Swaminathan ,  Zhichao Zhang ,  John M. Lynch ,  David J. Llapitan ,  Sanka Ganesan ,  Xiang Li ,  George Vergis

IPC分类号： H05K1/18 ,  H01R12/72 ,  H05K1/11 ,  H05K1/02 ,  H05K3/30 ,  H05K3/34

CPC分类号： H05K1/181 ,  H01L23/00 ,  H01L23/498 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01R12/712 ,  H01R12/79 ,  H05K2201/10159 ,  H05K2201/10325 ,  Y02P70/611

摘要： Configurable central processing unit (CPU) package substrates are disclosed. A package substrate is described that includes a processing device interface. The package substrate also includes a memory device electrical interface disposed on the package substrate. The package substrate also includes a removable memory mechanical interface disposed proximately to the memory device electrical interface. The removable memory mechanical interface is to allow a memory device to be easily removed from the package substrate after attachment of the memory device to the package substrate.

摘要翻译： 公开了可配置的中央处理单元（CPU）封装基板。 描述了包括处理设备接口的封装衬底。 封装衬底还包括设置在封装衬底上的存储器件电接口。 封装衬底还包括靠近存储器件电接口设置的可移除存储器机械接口。 可移除存储器机械接口是允许在将存储器件附接到封装衬底之后容易地从封装衬底移除存储器件。

公开(公告)号：US20160240949A1

公开(公告)日：2016-08-18

申请号：US15135413

申请日：2016-04-21

申请人： Sanka Ganesan ,  Ram S. Viswanath

发明人： Sanka Ganesan ,  Ram S. Viswanath

IPC分类号： H01R12/79 ,  H05K1/14 ,  H01L23/367 ,  H01L23/498 ,  H01L23/00

CPC分类号： H01R12/79 ,  H01B7/04 ,  H01L23/3675 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/17 ,  H01L24/72 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01R12/62 ,  H05K1/142 ,  H05K1/147 ,  H05K3/361 ,  H05K2201/10318 ,  H05K2201/10325 ,  H05K2201/10424 ,  H05K2201/10674 ,  H05K2201/10681 ,  H05K2201/2009 ,  H01L2224/0401

摘要： An integrated circuit package is presented. In an embodiment, the integrated circuit package has contact pads formed on the top side of a package substrate, a die electrically attached to the contact pads, and input/output (I/O) pads formed on the top side of the package substrate. The I/O pads are electrically connected to the contact pads. The integrated circuit package also includes a flex cable receptacle electrically connected to the I/O pads on the top side of the package substrate. The flex cable receptacle is non-compressively attachable to a flex cable connector and includes receptacle connection pins electrically connected to the I/O pads.

摘要翻译： 介绍了一种集成电路封装。 在一个实施例中，集成电路封装具有形成在封装基板的顶侧上的接触焊盘，电连接到接触焊盘的管芯，以及形成在封装基板的顶侧上的输入/输出（I / O）焊盘。 I / O焊盘电连接到接触焊盘。 集成电路封装还包括电连接到封装衬底的顶侧上的I / O焊盘的挠性电缆插座。 柔性电缆插座不可压缩地附接到柔性电缆连接器，并且包括电连接到I / O焊盘的插座连接引脚。

公开(公告)号：US09324678B2

公开(公告)日：2016-04-26

申请号：US13996498

申请日：2011-12-20

申请人： Sanka Ganesan ,  Ram S. Viswanath

发明人： Sanka Ganesan ,  Ram S. Viswanath

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L23/40 ,  H01L23/00 ,  H01R12/62 ,  H05K3/36 ,  H01L23/498 ,  H01B7/04 ,  H05K1/14

CPC分类号： H01R12/79 ,  H01B7/04 ,  H01L23/3675 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/17 ,  H01L24/72 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01R12/62 ,  H05K1/142 ,  H05K1/147 ,  H05K3/361 ,  H05K2201/10318 ,  H05K2201/10325 ,  H05K2201/10424 ,  H05K2201/10674 ,  H05K2201/10681 ,  H05K2201/2009 ,  H01L2224/0401

摘要： An integrated circuit package is presented. In an embodiment, the integrated circuit package has contact pads formed on the top side of a package substrate, a die electrically attached to the contact pads, and input/output (I/O) pads formed on the top side of the package substrate. The I/O pads are electrically connected to the contact pads. The integrated circuit package also includes a flex cable receptacle electrically connected to the I/O pads on the top side of the package substrate. The flex cable receptacle is non-compressively attachable to a flex cable connector and includes receptacle connection pins electrically connected to the I/O pads.

摘要翻译： 介绍了一种集成电路封装。 在一个实施例中，集成电路封装具有形成在封装基板的顶侧上的接触焊盘，电连接到接触焊盘的管芯，以及形成在封装基板的顶侧上的输入/输出（I / O）焊盘。 I / O焊盘电连接到接触焊盘。 集成电路封装还包括电连接到封装衬底的顶侧上的I / O焊盘的挠性电缆插座。 柔性电缆插座不可压缩地附接到柔性电缆连接器，并且包括电连接到I / O焊盘的插座连接引脚。

公开(公告)号：US10170409B2

公开(公告)日：2019-01-01

申请号：US15037276

申请日：2013-12-23

申请人： Sanka Ganesan ,  John S. Guzek ,  Nitesh Nimkar ,  Klaus Reingruber ,  Thorsten Meyer

发明人： Sanka Ganesan ,  John S. Guzek ,  Nitesh Nimkar ,  Klaus Reingruber ,  Thorsten Meyer

IPC分类号： H01L23/02 ,  H01L23/52 ,  H01L23/522 ,  H01L21/56 ,  H01L21/768 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10 ,  H01L25/00 ,  H01L23/31 ,  H01L23/538

摘要： Embodiments of the present disclosure are directed to package assemblies and methods for fabricating package assemblies. In one embodiment, a package assembly includes a die at least partially embedded in a mold compound; and a through mold via (TMV). The TMV may have vertical sides or may include two different portions with varying shapes. In some instances, prefabricated via bars may be used during fabrication. Package assemblies of the present disclosure may include package-on-package (POP) interconnects having a pitch of less than 0.3 mm. Other embodiments may be described and/or claimed.

公开(公告)号：US20130335939A1

公开(公告)日：2013-12-19

申请号：US13992791

申请日：2011-12-06

申请人： Aleksandar Aleksov ,  Sanka Ganesan

发明人： Aleksandar Aleksov ,  Sanka Ganesan

IPC分类号： B81B7/00

CPC分类号： B81B7/0006 ,  B23K35/0288 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/1132 ,  H01L2224/11474 ,  H01L2224/11849 ,  H01L2224/11903 ,  H01L2224/13012 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/14177 ,  H01L2224/14179 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81815 ,  H01L2924/01322 ,  H01L2924/3511 ,  H05K3/3436 ,  H05K2201/09418 ,  H05K2201/10734 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00

摘要： The present description relates to the field of fabricating microelectronic assemblies, wherein a microelectronic device may be attached to a microelectronic substrate with a plurality of shaped and oriented solder joints. The shaped and oriented solder joints may be substantially oval, wherein the major axis of the substantially oval solder joints may be substantially oriented toward a neutral point or center of the microelectronic device. Embodiments of the shaped and oriented solder joint may reduce the potential of solder joint failure due to stresses, such as from thermal expansion stresses between the microelectronic device and the microelectronic substrate.

摘要翻译： 本说明书涉及制造微电子组件的领域，其中微电子器件可以附接到具有多个成形和取向的焊点的微电子衬底。 成形和定向的焊接接头可以是基本上椭圆形的，其中基本上椭圆形焊点的长轴可以基本上朝向微电子器件的中性点或中心定向。 成形和取向的焊接接头的实施例可以减少由于应力（例如来自微电子器件和微电子衬底之间的热膨胀应力）引起的焊点故障的可能性。

公开(公告)号：US08353101B2

公开(公告)日：2013-01-15

申请号：US13008849

申请日：2011-01-18

申请人： Charan Gurumurthy ,  Sanka Ganesan ,  Chandrashekar Ramaswamy ,  Mark Hlad

发明人： Charan Gurumurthy ,  Sanka Ganesan ,  Chandrashekar Ramaswamy ,  Mark Hlad

IPC分类号： H05K3/00 ,  H01L21/46

CPC分类号： H01L23/48 ,  H01L23/49827 ,  H01L24/16 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H05K1/113 ,  H05K3/00 ,  H05K3/108 ,  H05K3/222 ,  H05K3/426 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/09509 ,  H05K2201/10189 ,  H05K2201/10356 ,  H05K2201/1053 ,  H05K2201/10734 ,  H05K2203/167 ,  Y10T29/49124 ,  H01L2224/0401

摘要： An assembly of substrate packages interconnected with flex cables and a method of fabrication of the substrate package. The assembly allows input/output (I/O) signals to be speedily transmitted between substrate packages via flex cable and without being routed through the motherboard. Embodiments relate to a substrate package providing separable inter-package flex cable connection. Hermetically-sealed guiding through holes are provided on the substrate package as a mechanical alignment feature to guide connection between flex cables and high speed I/O contact pads on the substrate package. Embodiments of the method of fabrication relate to simultaneously forming hermetically-sealed guiding through holes and I/O contact pads.

摘要翻译： 与柔性电缆互连的衬底封装的组件和衬底封装的制造方法。 该组件允许通过柔性电缆快速地在衬底封装之间传输输入/输出（I / O）信号，而不通过主板。 实施例涉及提供可分离的包装间柔性电缆连接的衬底封装。 在基板封装上提供密封导向孔，作为机械对准特征，以引导柔性电缆与基板封装上的高速I / O接触焊盘之间的连接。 制造方法的实施例涉及同时形成密封的引导通孔和I / O接触垫。