公开(公告)号：US06489613B1

公开(公告)日：2002-12-03

申请号：US09387878

申请日：1999-09-01

Applicant: Toru Mori ,  Katsuya Kawano

Inventor： Toru Mori ,  Katsuya Kawano

IPC: H01L3109

CPC classification number: H01L37/00 ,  G01J5/20 ,  H01L21/02565 ,  H01L21/02581

Abstract: An oxide thin film for bolometer having a vanadium oxide represented by VOx, where x satisfies 1.5≦x≦2.0, part of vanadium ion in the vanadium oxide being substituted by metal ion M, where the metal ion M is at least one of chromium (Cr), aluminum (Al), iron (Fe), manganese (Mn), niobium (Nb), tantalum (Ta) and titanium (Ti). Also, provided is an infrared detector having a bolometer thin film defined above. The oxide thin film for bolometer offers a low resistivity and a large TCR value. Also, the infrared detector offers a finer temperature resolution capability (NETD) as low as 0.03° C.

Abstract translation: 一种用于具有由VOx表示的氧化钒的测辐射热计的氧化物薄膜，其中x满足1.5 <= x <= 2.0，氧化钒中的钒离子的一部分被金属离子M取代，其中金属离子M是 铬（Cr），铝（Al），铁（Fe），锰（Mn），铌（Nb），钽（Ta）和钛（Ti）。 而且，提供了一种具有上述定影仪薄膜的红外检测器。 测辐射热计的氧化物薄膜具有低电阻率和较大的TCR值。 此外，红外检测器可提供低至0.03°C的更精细的温度分辨能力（NETD）。

公开(公告)号：US5633215A

公开(公告)日：1997-05-27

申请号：US601586

申请日：1996-02-14

Applicant: Toru Mori

Inventor： Toru Mori

IPC: C04B35/00 ,  C04B35/49 ,  C04B35/495 ,  C04B35/499 ,  H01B3/12 ,  H01G4/12 ,  C04B35/46 ,  C04B35/472

CPC classification number: C04B35/495 ,  C04B35/499

Abstract: A dielectric porcelain composition includes lead magnesium tungstate (Pb(Mg.sub.1/2 W.sub.1/2)O.sub.3), lead titanate (PbTiO.sub.3) and lead zirconate (PbZrO.sub.3) as main components at composition ratios of x, y and z respectively, wherein a point (x, y, z) in a ternary system is positioned on or within a boundary which comprises four straight line segments defined by four points of (0.725, 0.25, 0.025), (0.45, 0.525, 0.025), (0.30, 0.30, 0.40) and (0.475, 0.125, 0.40) in said ternary system as illustrated in FIG. 1, and wherein said main components are added with at least one rare earth oxide at a molar ratio in the range of 0.1-5.0 mol %.

Abstract translation: 电介质陶瓷组合物包括钨酸铅镁（Pb（Mg + E，fra 1/2 + EE W + E，fra 1/2 + EE）O 3），钛酸铅（PbTiO 3）和锆酸铅（PbZrO 3） 分别为x，y和z的组成比，其中三元系统中的点（x，y，z）位于包含由（0.725,0.25,0.025）的四个点定义的四个直线段的边界上或内部， （0.45,0.525,0.025），（0.30,0.30,0.40）和（0.475,0.125,0.40），如图3所示。 1，其中所述主要组分以0.1-5.0摩尔％的摩尔比加入至少一种稀土氧化物。

公开(公告)号：US08273646B2

公开(公告)日：2012-09-25

申请号：US13064204

申请日：2011-03-10

Applicant: Toru Mori

Inventor： Toru Mori

IPC: H01L21/28 ,  H01L29/788 ,  H01L29/423

CPC classification number: H01L29/792 ,  H01L27/105 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/66833

Abstract: A non-volatile memory device includes a memory cell region which is formed on a semiconductor substrate to store predetermined information, and a peripheral circuit region which is formed on the semiconductor substrate. The memory cell region includes a gate electrode; and a charge storage layer, the charge storage layer being formed to be a notch or wedge shape having an edge extending into both sides of a bottom end of the gate electrode. The peripheral circuit region includes no charge storage layer therein.

Abstract translation: 非易失性存储器件包括形成在半导体衬底上以存储预定信息的存储单元区域和形成在半导体衬底上的外围电路区域。 存储单元区域包括栅电极; 和电荷存储层，所述电荷存储层形成为具有延伸到所述栅电极的底端的两侧的边缘的凹口或楔形。 外围电路区域中不包含电荷存储层。

公开(公告)号：US20120108304A1

公开(公告)日：2012-05-03

申请号：US13329823

申请日：2011-12-19

Applicant: Satoshi Horie ,  Atsushi Ueno ,  Toru Mori ,  Yuichiro Murotsuka ,  Masahiro Mihara

Inventor： Satoshi Horie ,  Atsushi Ueno ,  Toru Mori ,  Yuichiro Murotsuka ,  Masahiro Mihara

IPC: A63F9/24

CPC classification number: A63F1/04 ,  A63F2009/2407 ,  A63F2009/241 ,  A63F2009/2438 ,  A63F2009/2458 ,  A63F2009/246 ,  A63F2009/2486

Abstract: A game device is provided that can reduce the size of the device and can execute the simulation of a match game scene based on an operation input by a game player. The game device includes a field panel imitating a field of a sporting event, card holding stages that are arranged in the locations indicating the positions of players in the sporting event on the field panel, and holding card in a raised state, a card information reading means for reading card information recorded on the cards held by the card holding stages, and a game execution control means for controlling the execution of a game.

Abstract translation: 提供一种游戏装置，其可以减小装置的尺寸，并且可以基于游戏者输入的操作来执行匹配游戏场景的模拟。 游戏装置包括模拟体育赛事场地的场地面板，卡片保持阶段，其布置在指示场地面板上的运动事件中的玩家的位置的位置，以及保持卡处于升高状态，卡片信息读取 用于读取记录在由卡片保持阶段保持的卡上的卡片信息的装置，以及用于控制游戏执行的游戏执行控制装置。

公开(公告)号：US20100044089A1

公开(公告)日：2010-02-25

申请号：US12529378

申请日：2008-02-28

Applicant: Akinobu Shibuya ,  Yasuhiro Ishii ,  Toru Mori ,  Koichi Takemura

Inventor： Akinobu Shibuya ,  Yasuhiro Ishii ,  Toru Mori ,  Koichi Takemura

IPC: H05K1/16 ,  H05K3/30

CPC classification number: H05K1/162 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L27/016 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/0102 ,  H01L2924/01025 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H05K3/4614 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2201/09763 ,  H05K2201/10378 ,  H05K2203/061 ,  Y10T29/4913 ,  H01L2924/00014

Abstract: An interposer integrated with capacitors (100) includes a plug substrate (10) in which via-plugs (12) is formed, and a capacitor substrate (20) in which capacitors are formed. The capacitor substrate (20) includes a substrate body (21), capacitors (22) formed on the main surface of the substrate body, a cover insulating film (25) that covers the capacitors, a terminal electrodes (26) connected to the electrodes of the capacitor and formed on the cover insulating film, electrode pads (24) formed on the rear surface of the substrate body, and via-plugs 23 connecting together the terminal electrodes and electrode pads. The plug substrate (10) includes a substrate body (11), and electrode pads (13) formed on the main surface of the substrate body corresponding to the terminal electrodes of the capacitor substrate, and via-plugs (12) penetrating the substrate body and connected to the electrode pads.

Abstract translation: 与电容器（100）集成的插入器包括其中形成有通孔（12）的插头基板（10）和形成有电容器的电容器基板（20）。 电容器基板（20）包括基板主体（21），形成在基板主体的主表面上的电容器（22），覆盖电容器的覆盖绝缘膜（25），与电极连接的端子电极 的电容器，形成在覆盖绝缘膜上，形成在基板主体的后表面上的电极焊盘（24）以及将端子电极和电极焊盘连接在一起的通孔塞23。 插头基板（10）包括基板主体（11），和形成在基板主体的与主电极基板的端子电极对应的主面上的电极焊盘（13）以及穿过基板体的通孔（12） 并连接到电极焊盘。

公开(公告)号：US20090233230A1

公开(公告)日：2009-09-17

申请号：US11989124

申请日：2005-07-22

Applicant: Yosuke Hata ,  Toru Mori

Inventor： Yosuke Hata ,  Toru Mori

IPC: G03F7/20 ,  G03F7/004

CPC classification number: C08F290/06 ,  C08F290/061 ,  C08L53/00 ,  C09D133/08 ,  G03F7/031 ,  G03F7/033 ,  C08L2666/02

Abstract: The present invention provides a photosensitive resin composition characterized by comprising: (a) 20 to 90% by mass of a thermoplastic copolymer comprising an α,β-unsaturated carboxyl group containing monomer as a copolymerization constituent and having an acid equivalent of 100 to 600 and a weight-average molecular weight of 5000 to 500000; (b) 5 to 75% by mass of an addition polymerizable monomer having at least one terminal ethylenic unsaturated group; (c) 0.01 to 30% by mass of a photopolymerization initiator containing a hexaarylbisimidazole; and (d) 0.001 to 10% by mass of a pyrazoline compound represented by the following general formula (I): (wherein A, B, and C each independently represent a substituent selected from the group consisting of an aryl group, a heterocyclic group, a linear or branched alkyl group having 3 or more carbon atoms, and NR2 (R represents a hydrogen atom or an alkyl group); and each of a, b, and c represents an integer of 0 to 2, provide that the value of a+b+c is 1 or larger).

Abstract translation: 本发明提供一种感光性树脂组合物，其特征在于，包含：（a）20〜90质量％的含有α，β-不饱和羧基的单体作为共聚成分，酸当量为100〜600的热塑性共聚物， 重均分子量为5000〜500000; （b）5〜75质量％的具有至少一个末端烯属不饱和基团的加成聚合性单体; （c）0.01〜30质量％的含有六芳基双咪唑的光聚合引发剂; 和（d）0.001〜10质量％的由以下通式（I）表示的吡唑啉化合物：（其中A，B和C各自独立地表示选自芳基，杂环基 ，具有3个以上碳原子的直链或支链烷基，NR2（R表示氢原子或烷基），a，b，c分别表示0〜2的整数， a + b + c为1以上）。

公开(公告)号：US07115964B2

公开(公告)日：2006-10-03

申请号：US11134391

申请日：2005-05-23

Applicant: Toru Mori

Inventor： Toru Mori

IPC: H01L29/00

CPC classification number: H01L29/66772 ,  H01L29/41733 ,  H01L29/78639 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A manufacturing method for an SOI semiconductor device includes creating transistors and an element isolation region on a semiconductor layer in an SOI substrate. The method also includes covering the transistors and the element isolation region with a first insulation film. The method also includes creating a first opening section which penetrates the first insulation film, element isolation region and a buried oxide film to expose the support substrate. The method also includes creating a first source interconnect, first drain interconnect and first gate interconnect which are electrically connected to the transistors, on the second insulation film. The method also includes forming dummy interconnects which are connected with these interconnects, and are electrically connected with the support substrate via the first opening section, on the second insulation film. The method also includes disconnecting the dummy interconnects to electrically insulate the first source interconnect, first drain interconnect and first gate interconnect from the support substrate.

Abstract translation: SOI半导体器件的制造方法包括在SOI衬底中的半导体层上产生晶体管和元件隔离区域。 该方法还包括用第一绝缘膜覆盖晶体管和元件隔离区域。 该方法还包括形成穿透第一绝缘膜，元件隔离区域和掩埋氧化膜以暴露支撑衬底的第一开口部分。 该方法还包括在第二绝缘膜上形成电连接到晶体管的第一源极互连，第一漏极互连和第一栅极互连。 该方法还包括形成与这些互连连接的虚拟互连件，并且经由第一开口部分在第二绝缘膜上与支撑基板电连接。 该方法还包括断开虚拟互连以将第一源互连，第一漏互连和第一栅互连与支撑衬底电绝缘。

公开(公告)号：US06949815B2

公开(公告)日：2005-09-27

申请号：US10746603

申请日：2003-12-23

Applicant: Takao Yamazaki ,  Toru Mori ,  Akinobu Shibuya ,  Shintaro Yamamichi ,  Yuzo Shimada

Inventor： Takao Yamazaki ,  Toru Mori ,  Akinobu Shibuya ,  Shintaro Yamamichi ,  Yuzo Shimada

IPC: H05K3/34 ,  H01L21/60 ,  H01L21/822 ,  H01L23/12 ,  H01L23/50 ,  H01L23/64 ,  H01L27/04 ,  H01L23/52 ,  H01L23/32 ,  H01L23/48 ,  H01G9/05

CPC classification number: H01L24/81 ,  H01L23/50 ,  H01L23/642 ,  H01L24/73 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/30105 ,  H01L2924/30107

Abstract: A semiconductor device has an LSI device provided with a plurality of power supply line connection pads and ground line connection pad in a peripheral edge part of a circuit-formation surface, metal foil leads 5 electrically connected to each of the pads and adhered to the LSI device via an insulation layer, and decoupling capacitors mounted on one surface of the metal foil leads.

Abstract translation: 半导体器件具有在电路形成面的周边部分设置有多个电源线连接焊盘和接地线连接焊盘的LSI器件，电连接到每个焊盘并粘附到LSI的金属箔引线5 通过绝缘层的器件，以及安装在金属箔引线的一个表面上的去耦电容器。

公开(公告)号：US06365828B1

公开(公告)日：2002-04-02

申请号：US09691257

申请日：2000-10-19

Applicant: Yasushi Kinoshita ,  Hiroshi Wabuka ,  Shiro Yoshida ,  Hirokazu Tohya ,  Toru Mori ,  Atsushi Ochi

Inventor： Yasushi Kinoshita ,  Hiroshi Wabuka ,  Shiro Yoshida ,  Hirokazu Tohya ,  Toru Mori ,  Atsushi Ochi

IPC: H05K900

CPC classification number: H05K1/165 ,  H01L23/552 ,  H01L23/585 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K1/162 ,  H05K7/1092 ,  H05K9/0066 ,  H05K2201/1006 ,  H05K2201/10689 ,  H01L2924/00

Abstract: The electromagnetic interference suppressing device of the present invention includes a plurality of connection layers and ground layers formed of a conductive material. The connection layers and the ground layers are alternately layered. Insulating layers, formed of an insulating material, intervene between the neighboring connection layers and ground layers. The odd connection layers counting from the bottom and the connection layers just above those layers are electrically connected at the same end. The even connection layers counting from the bottom and the connection layers just above those layers are electrically connected at the same end opposite to the odd connection-layered end. The bottommost connection layer is connected to a first signal terminal. The uppermost connection layer is connected to a second signal terminal. The ground layer is connected to a ground terminal.

Abstract translation: 本发明的电磁干扰抑制装置包括多个连接层和由导电材料形成的接地层。 连接层和接地层交替层叠。 由绝缘材料形成的绝缘层介于相邻连接层和接地层之间。 从底部计数的奇数连接层和正好在这些层上方的连接层在同一端电连接。 从底部开始计数的连接层和刚好在这些层上方的连接层在与奇数连接分层端相反的相同端部电连接。 最下面的连接层连接到第一信号端子。 最上面的连接层连接到第二信号端子。 接地层连接到接地端子。

公开(公告)号：US06338048B1

公开(公告)日：2002-01-08

申请号：US09254706

申请日：1999-03-12

Applicant: Toru Mori

Inventor： Toru Mori

IPC: G06K500

CPC classification number: G07F7/0866 ,  G06Q20/00 ,  G06Q20/105 ,  G06Q20/363

Abstract: A plurality of types of settlement conditions exist for transactions with electronic money. An electronic transaction system capable of being applied to a plurality of types of settlement conditions using a single automatic teller machine is provided. In order to achieve this, this system has the following configuration. Namely, in this electronic transaction system for carrying out transaction settlements using electronic money stored on a customer card while using an automatic teller machine, customer identification information and an electronic money amount are stored as balance information for each customer account established at a financial institution, with the customer card being such that stored information can be updated based on pre-decided transaction conditions. The automatic teller machine then houses customer cards corresponding to a plurality of transaction conditions and a plurality of ATM cards, and a plurality of control software is prepared. Control software coinciding with the transaction conditions is then activated, and transactions are carried out with the ATM cards stored in the automatic teller machine.

Abstract translation: 存在用于与电子货币进行交易的多种类型的结算条件。 提供一种能够使用单个自动取款机应用于多种类型的结算条件的电子交易系统。 为了实现这一点，该系统具有以下配置。 也就是说，在使用自动提款机的电子货币使用电子货币进行交易结算的电子交易系统中，客户识别信息和电子货币金额被存储为在金融机构建立的每个客户账户的余额信息， 客户卡可以使得存储的信息可以基于预先确定的交易条件来更新。 然后，自动柜员机容纳对应于多个交易条件的客户卡和多个ATM卡，并且准备了多个控制软件。 然后激活与交易条件相符的控制软件，并且使用存储在自动柜员机中的ATM卡进行交易。