公开(公告)号：US20100267229A1

公开(公告)日：2010-10-21

申请号：US12828082

申请日：2010-06-30

申请人： Fritz Redeker ,  John Boyd ,  Yezdi Dordi ,  Hyungsuk Alexander Yoon ,  Shijian Li

发明人： Fritz Redeker ,  John Boyd ,  Yezdi Dordi ,  Hyungsuk Alexander Yoon ,  Shijian Li

IPC分类号： H01L21/768

CPC分类号： C25D7/123 ,  C23C18/1653 ,  C23C28/023 ,  C23C28/322 ,  C23C28/34 ,  C23C28/341 ,  H01L21/28562 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76862 ,  H01L21/76873 ,  H01L21/76874 ,  H01L23/53238 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to methods and systems for the metallization of semiconductor devices. One aspect of the present invention is a method of depositing a copper layer onto a barrier layer so as to produce a substantially oxygen free interface therebetween. In one embodiment, the method includes providing a substantially oxide free surface of the barrier layer. The method also includes depositing an amount of atomic layer deposition (ALD) copper on the oxide free surface of the barrier layer effective to prevent oxidation of the barrier layer. The method further includes depositing a gapfill copper layer over the ALD copper. Another aspect of the present invention is a system for depositing a copper layer onto barrier layer so as to produce a substantially oxygen-free interface therebetween. In one embodiment, the integrated system includes at least one barrier deposition module. The system also includes an ALD copper deposition module configured to deposit copper by atomic layer deposition. The system further includes a copper gapfill module and at least one transfer module coupled to the at least one barrier deposition module and to the ALD copper deposition module. The transfer module is configured so that the substrate can be transferred between the modules substantially without exposure to an oxide-forming environment.

摘要翻译： 本发明涉及用于半导体器件金属化的方法和系统。 本发明的一个方面是将铜层沉积在阻挡层上以在其间产生基本上无氧的界面的方法。 在一个实施例中，该方法包括提供阻挡层的基本上无氧化物的表面。 该方法还包括在阻挡层的无氧化物表面上沉积一定量的原子层沉积（ALD）铜，以有效地防止阻挡层的氧化。 该方法还包括在ALD铜上沉积间隙填充铜层。 本发明的另一方面是一种用于在阻挡层上沉积铜层以在其间产生基本上无氧的界面的系统。 在一个实施例中，集成系统包括至少一个阻挡层沉积模块。 该系统还包括配置为通过原子层沉积沉积铜的ALD铜沉积模块。 该系统还包括铜间隙填充模块和耦合到至少一个阻挡层沉积模块和ALD铜沉积模块的至少一个传输模块。 转移模块被配置为使得基板可以在基本上不暴露于氧化物形成环境的基础之间传递。

公开(公告)号：US07615480B2

公开(公告)日：2009-11-10

申请号：US11820811

申请日：2007-06-20

申请人： John Boyd ,  Fritz Redeker ,  Yezdi Dordi ,  Hyungsuk Alexander Yoon ,  Shijian Li

发明人： John Boyd ,  Fritz Redeker ,  Yezdi Dordi ,  Hyungsuk Alexander Yoon ,  Shijian Li

IPC分类号： H01L21/20

CPC分类号： H01L23/48 ,  H01L21/4763 ,  H01L21/76898 ,  H01L2924/14

摘要： Presented are methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. In one embodiment, the method comprises forming metal plug contacts through a hard mask and a premetal dielectric to transistors in the semiconductor. The method also includes etching a hole for a through-hole via through the hard mask to the semiconductor using a patterned photoresist process, removing the patterned photoresist and using a hard mask process to etch the hole to an amount into the semiconductor. The method further includes depositing a dielectric liner to isolate the hole from the semiconductor, depositing a gapfill metal to fill the hole, and planarizing the surface of the substrate to the hard mask. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention.

摘要翻译： 提出了制造三维集成电路的方法，其包括用于三维集成电路的集成的线路通孔的后接触后端。 在一个实施例中，该方法包括通过硬掩模和前金属电介质形成金属插头触点到半导体中的晶体管。 该方法还包括使用图案化的光致抗蚀剂工艺将用于通孔的通孔穿过硬掩模蚀刻到半导体，去除图案化的光致抗蚀剂并使用硬掩模工艺将孔蚀刻到半导体中的量。 所述方法还包括沉积介电衬垫以将所述孔与所述半导体隔离，沉积间隙填充金属以填充所述孔，以及将所述衬底的表面平面化至所述硬掩模。 本发明的另一方面包括根据本发明的方法制造的三维集成电路。

公开(公告)号：US20080315422A1

公开(公告)日：2008-12-25

申请号：US11821051

申请日：2007-06-20

申请人： John Boyd ,  Fritz Redeker ,  Yezdi Dordi ,  Hyungsuk Alexander Yoon ,  Shijian Li

发明人： John Boyd ,  Fritz Redeker ,  Yezdi Dordi ,  Hyungsuk Alexander Yoon ,  Shijian Li

IPC分类号： H01L21/4763 ,  H01L21/44 ,  H01L23/48

CPC分类号： H01L21/44 ,  H01L21/76898 ,  H01L23/48 ,  H01L23/481 ,  H01L25/50 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods and apparatuses for fabricating three-dimensional integrated circuits having through hole vias are provided. One aspect of the present invention is a method of gapfill for through hole vias for three-dimensional integrated circuits. The method comprises providing a semiconductor wafer having a plurality of holes for through hole vias and depositing a conformal metal layer to partially fill the holes to leave open voids. The method also includes purging the voids and cleaning the surface of the voids and using a dry deposition process to fill or close the voids. Another aspect of the present invention is an electronic device structure for a three-dimensional integrated circuit.

摘要翻译： 提供了具有通孔的三维集成电路的制造方法和装置。 本发明的一个方面是用于三维集成电路的通孔通孔的间隙填充方法。 该方法包括提供具有用于通孔通孔的多个孔的半导体晶片，并且沉积保形金属层以部分填充孔以留下开孔。 该方法还包括清除空隙并清洁空隙的表面，并使用干式沉积工艺填充或封闭空隙。 本发明的另一方面是一种用于三维集成电路的电子设备结构。

公开(公告)号：US20080314756A1

公开(公告)日：2008-12-25

申请号：US11820810

申请日：2007-06-20

申请人： John Boyd ,  Fritz Redeker ,  Yezdi Dordi ,  Hyungsuk Alexander Yoon ,  Shijian Li

发明人： John Boyd ,  Fritz Redeker ,  Yezdi Dordi ,  Hyungsuk Alexander Yoon ,  Shijian Li

IPC分类号： C25D3/38 ,  C25D3/00

CPC分类号： C25D3/00 ,  H01L21/2885 ,  H01L21/32115 ,  H01L21/67005 ,  H01L21/67023 ,  H01L21/67075 ,  H01L21/6708 ,  H01L21/6715 ,  H01L21/768 ,  H01L21/7684 ,  H01L21/76883 ,  H01L21/76898

摘要： Presented are methods and systems for fabricating three-dimensional integrated circuits having large diameter through-hole vias. One embodiment of the present invention provides a method of processing a wafer having holes for through-hole vias. The method comprises plating a gapfill metal on the wafer. The method also comprises chemically or electrochemically deplating a portion of the overburden metal. The method further comprises using chemical mechanical planarization to planarize the gapfill metal and to remove the remaining overburden metal. Another embodiment of the present invention is an integrated system comprising a process chamber for containing the wafer, a plating component integrated with the process chamber, and a deplating component integrated with the process chamber. The plating component is configured to electrochemically plate a gapfill metal onto the wafer to a least partially fill the holes. The deplating component is configured to chemically or to electrochemically remove a portion of the overburden metal formed by the plating component.

摘要翻译： 提出了用于制造具有大直径通孔的三维集成电路的方法和系统。 本发明的一个实施例提供一种处理具有用于通孔过孔的孔的晶片的方法。 该方法包括在晶片上镀覆间隙填充金属。 该方法还包括化学地或电化学地去除一部分覆盖层金属。 该方法还包括使用化学机械平面化来平坦化间隙填充金属并除去剩余的覆盖层金属。 本发明的另一实施例是一种集成系统，其包括用于容纳晶片的处理室，与处理室一体化的电镀部件，以及与处理室一体化的去掉部件。 电镀部件被配置为将间隙填充金属电化学地平板化到晶片上以至少部分地填充孔。 脱镀部件被配置为化学地或电化学地去除由电镀部件形成的覆盖层金属的一部分。

公开(公告)号：US20080280456A1

公开(公告)日：2008-11-13

申请号：US11801269

申请日：2007-05-08

申请人： Zhonghui Alex Wang ,  Tiruchirapalli Arunagiri ,  Fritz C. Redeker ,  Yezdi Dordi ,  John Boyd ,  Mikhail Korolik ,  Arthur M. Howald ,  William Thie ,  Praveen Nalla

发明人： Zhonghui Alex Wang ,  Tiruchirapalli Arunagiri ,  Fritz C. Redeker ,  Yezdi Dordi ,  John Boyd ,  Mikhail Korolik ,  Arthur M. Howald ,  William Thie ,  Praveen Nalla

IPC分类号： H01L21/00

CPC分类号： H01L21/02074

摘要： Methods for cleaning semiconductor wafers following chemical mechanical polishing are provided. An exemplary method exposes a wafer to a thermal treatment in an oxidizing environment followed by a thermal treatment in a reducing environment. The thermal treatment in the oxidizing environment both removes residues and oxidizes exposed copper surfaces to form a cupric oxide layer. The thermal treatment in the reducing environment then reduces the cupric oxide to elemental copper. This leaves the exposed copper clean and in condition for further processing, such as electroless plating.

摘要翻译： 提供了化学机械抛光后的半导体晶片清洗方法。 一种示例性方法将晶片暴露于氧化环境中的热处理，然后在还原环境中进行热处理。 在氧化环境中的热处理既去除残留物，又氧化暴露的铜表面以形成氧化铜层。 然后，在还原环境中的热处理将氧化铜还原为元素铜。 这使得暴露的铜清洁并进行进一步处理，例如化学镀。

公开(公告)号：US20080152823A1

公开(公告)日：2008-06-26

申请号：US11643404

申请日：2006-12-20

申请人： John Boyd ,  Yezdi Dordi ,  Tiruchirapalli Arunagiri ,  William Thie ,  Fritz C. Redeker ,  Praveen Nalla

发明人： John Boyd ,  Yezdi Dordi ,  Tiruchirapalli Arunagiri ,  William Thie ,  Fritz C. Redeker ,  Praveen Nalla

IPC分类号： B05D1/18

CPC分类号： C23C18/1689 ,  C23C18/161 ,  C23C18/1653 ,  C23C18/1658 ,  C23C18/1683 ,  C23C18/31 ,  H01L21/288 ,  H01L21/76877

摘要： A self-limiting electroless plating process is provided to plate thin films with improved uniformity. The process comprises dispensing an electroless plating solution onto a substrate to form a quiescent solution layer from which a conformal plated layer plates onto a surface of the substrate by a redox reaction. The redox reaction occurs at the surface of the substrate between a reducing agent ion and a plating ion and produces an oxidized ion. Because the solution is quiescent, a boundary layer forms within the solution layer adjacent to the surface. The boundary layer is characterized by a concentration gradient of the oxidized ion. Diffusion of the reducing agent ion through the boundary layer controls the redox reaction. The quiescent solution layer can be maintained until the reducing agent ion in the solution layer is substantially depleted.

摘要翻译： 提供了一种自限制化学镀工艺，以平整薄膜，以均匀度提高。 该方法包括将化学镀溶液分配到基底上以形成静电溶液层，通过氧化还原反应从其中将共形镀层从该平板镀在基底的表面上。 氧化还原反应发生在还原剂离子和镀覆离子之间的衬底表面，并产生氧化离子。 因为溶液是静止的，所以在与表面相邻的溶液层内形成边界层。 边界层的特征在于氧化离子的浓度梯度。 还原剂离子通过边界层的扩散控制氧化还原反应。 可以维持静止溶液层，直到溶液层中的还原剂离子基本上被耗尽。

公开(公告)号：US20080142972A1

公开(公告)日：2008-06-19

申请号：US11641361

申请日：2006-12-18

申请人： Fritz Redeker ,  John Boyd ,  Yezdi Dordi ,  Hyungsuk Alexander Yoon ,  Shijian Li

发明人： Fritz Redeker ,  John Boyd ,  Yezdi Dordi ,  Hyungsuk Alexander Yoon ,  Shijian Li

IPC分类号： H01L21/4763 ,  H01L23/52 ,  C25D3/38

CPC分类号： C25D7/123 ,  C23C18/1653 ,  C23C28/023 ,  C23C28/322 ,  C23C28/34 ,  C23C28/341 ,  H01L21/28562 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76862 ,  H01L21/76873 ,  H01L21/76874 ,  H01L23/53238 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to methods and systems for the metallization of semiconductor devices. One aspect of the present invention is a method of depositing a copper layer onto a barrier layer so as to produce a substantially oxygen free interface therebetween. In one embodiment, the method includes providing a substantially oxide free surface of the barrier layer. The method also includes depositing an amount of atomic layer deposition (ALD) copper on the oxide free surface of the barrier layer effective to prevent oxidation of the barrier layer. The method further includes depositing a gapfill copper layer over the ALD copper. Another aspect of the present invention is a system for depositing a copper layer onto barrier layer so as to produce a substantially oxygen-free interface therebetween. In one embodiment, the integrated system includes at least one barrier deposition module. The system also includes an ALD copper deposition module configured to deposit copper by atomic layer deposition. The system further includes a copper gapfill module and at least one transfer module coupled to the at least one barrier deposition module and to the ALD copper deposition module. The transfer module is configured so that the substrate can be transferred between the modules substantially without exposure to an oxide-forming environment.

摘要翻译： 本发明涉及用于半导体器件金属化的方法和系统。 本发明的一个方面是将铜层沉积在阻挡层上以在其间产生基本上无氧的界面的方法。 在一个实施例中，该方法包括提供阻挡层的基本上无氧化物的表面。 该方法还包括在阻挡层的无氧化物表面上沉积一定量的原子层沉积（ALD）铜，以有效地防止阻挡层的氧化。 该方法还包括在ALD铜上沉积间隙填充铜层。 本发明的另一方面是一种用于在阻挡层上沉积铜层以在其间产生基本上无氧的界面的系统。 在一个实施例中，集成系统包括至少一个阻挡层沉积模块。 该系统还包括配置为通过原子层沉积沉积铜的ALD铜沉积模块。 该系统还包括铜间隙填充模块和耦合到至少一个阻挡层沉积模块和ALD铜沉积模块的至少一个传输模块。 转移模块被配置为使得基板可以在基本上不暴露于氧化物形成环境的基础之间传递。

公开(公告)号：US20080057198A1

公开(公告)日：2008-03-06

申请号：US11639050

申请日：2006-12-13

申请人： Hyungsuk Alexander Yoon ,  John Boyd ,  Yezdi Dordi ,  Fritz C. Redeker

发明人： Hyungsuk Alexander Yoon ,  John Boyd ,  Yezdi Dordi ,  Fritz C. Redeker

IPC分类号： C23C16/00 ,  B05D3/00 ,  B05D1/36

CPC分类号： H01L21/67196 ,  C23C14/22 ,  C23C16/06 ,  C23C16/44 ,  C23C16/45544 ,  C23C16/52 ,  C23C18/1619 ,  C23C18/1632 ,  C23C18/1653 ,  C23C18/38 ,  H01L21/0206 ,  H01L21/02063 ,  H01L21/02068 ,  H01L21/02074 ,  H01L21/288 ,  H01L21/321 ,  H01L21/32115 ,  H01L21/32135 ,  H01L21/32136 ,  H01L21/67028 ,  H01L21/67161 ,  H01L21/67201 ,  H01L21/67207 ,  H01L21/6723 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76861 ,  H01L21/76862 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76876 ,  H01L21/76879

摘要： The embodiments fill the need of improving electromigration and reducing stress-induced voids of copper interconnect by enabling deposition of a thin and conformal barrier layer, and a copper layer in the copper interconnect. The adhesion between the barrier layer and the copper layer can be improved by making the barrier layer metal-rich prior copper deposition and by limiting the amount of oxygen the barrier layer is exposed prior to copper deposition. Alternatively, a functionalization layer can be deposited over the barrier layer to enable the copper layer being deposit in the copper interconnect with good adhesion between the barrier layer and the copper layer. An exemplary method of preparing a substrate surface of a substrate to deposit a functionalization layer over a metallic barrier layer of a copper interconnect to assist deposition of a copper layer in the copper interconnect in an integrated system in order to improve electromigration performance of the copper interconnect is provided. The method includes depositing the metallic barrier layer to line the copper interconnect structure in the integrated system, wherein after depositing the metallic barrier layer, the substrate is transferred and processed in controlled environment to prevent the formation of metallic barrier oxide. The method also includes depositing the functionalization layer over the metallic layer in the integrated system. The method further includes depositing the copper layer in the copper interconnect structure in the integrated system after the functionalization layer is deposited over the metallic barrier layer.

摘要翻译： 实施例满足了通过能够在铜互连中沉积薄且保形的阻挡层和铜层来改善电迁移并减少铜互连的应力诱导空隙的需要。 阻挡层和铜层之间的粘附性可以通过在铜沉积之前使阻挡层富金属的先前铜沉积和限制阻挡层暴露的氧的量来改善。 或者，功能化层可以沉积在阻挡层上，以使得铜层能够在铜互连中沉积，并且在阻挡层和铜层之间具有良好的粘合性。 一种制备衬底的衬底表面以在铜互连的金属阻挡层上沉积功能化层以帮助在一个集成系统中铜层互连中铜层沉积以便改善铜互连的电迁移性能的示例性方法 被提供。 该方法包括沉积金属阻挡层以在集成系统中对铜互连结构进行排列，其中在沉积金属阻挡层之后，将基底在受控环境中转移和加工以防止形成金属阻挡氧化物。 该方法还包括在集成系统中的金属层上沉积功能化层。 该方法还包括在官能化层沉积在金属阻挡层上之后，在集成系统中的铜互连结构中沉积铜层。

公开(公告)号：US20080057182A1

公开(公告)日：2008-03-06

申请号：US11611758

申请日：2006-12-15

申请人： John Boyd ,  Yezdi Dordi ,  Tiruchirapalli Arunagiri ,  Benjamin Mooring ,  John Parks ,  William Thie ,  Fritz Redeker ,  Arthur Howald ,  Alan Schoepp ,  David Hemker

发明人： John Boyd ,  Yezdi Dordi ,  Tiruchirapalli Arunagiri ,  Benjamin Mooring ,  John Parks ,  William Thie ,  Fritz Redeker ,  Arthur Howald ,  Alan Schoepp ,  David Hemker

IPC分类号： B05D5/12 ,  B05D1/36

CPC分类号： H01L21/67207 ,  H01L21/76843 ,  H01L21/76877

摘要： A method for filling a trench of a substrate in a controlled environment is provided. The method initiates with etching a trench in the substrate in a first chamber of a cluster tool. A barrier layer configured to prevent electromigration is deposited over an exposed surface of the trench in a second chamber of the cluster tool and the trench is filled with a gap fill material deposited directly onto the barrier layer in the cluster tool. A semiconductor device fabricated by the method is also provided.

摘要翻译： 提供了一种用于在受控环境中填充衬底的沟槽的方法。 该方法通过在簇工具的第一室中蚀刻衬底中的沟槽来启动。 构造成防止电迁移的阻挡层沉积在簇工具的第二腔中的沟槽的暴露表面上，并且沟槽填充有直接沉积在簇工具中的阻挡层上的间隙填充材料。 还提供了通过该方法制造的半导体器件。

公开(公告)号：US20070292604A1

公开(公告)日：2007-12-20

申请号：US11513634

申请日：2006-08-30

申请人： Yezdi Dordi ,  John Boyd ,  Tiruchirapalli Arunagiri ,  Fritz C. Redeker ,  William Thie ,  Arthur M. Howald

发明人： Yezdi Dordi ,  John Boyd ,  Tiruchirapalli Arunagiri ,  Fritz C. Redeker ,  William Thie ,  Arthur M. Howald

IPC分类号： B05D3/00 ,  B05D5/12 ,  B05D1/18 ,  C04B41/00 ,  C23C14/00 ,  B05C13/02 ,  B29C71/04

CPC分类号： B05C13/02 ,  B05D3/002 ,  C23C18/1651 ,  C23C18/1851 ,  C23C18/1893 ,  H01L21/0206 ,  H01L21/02063 ,  H01L21/02068 ,  H01L21/02074 ,  H01L21/28518 ,  H01L21/288 ,  H01L21/32115 ,  H01L21/32135 ,  H01L21/32136 ,  H01L21/67161 ,  H01L21/67207 ,  H01L21/76814 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76862

摘要： The embodiments fill the need to enhance electro-migration performance, provide lower metal resistivity, and improve metal-to-metal interfacial adhesion for copper interconnects by providing improved processes and systems that produce an improved metal-to-metal interface, more specifically copper-to-cobalt-alloy interface. An exemplary method of preparing a substrate surface of a substrate to selectively deposit a thin layer of a cobalt-alloy material on a copper surface of a copper interconnect of the substrate in an integrated system to improve electromigration performance of the copper interconnect is provided. The method includes removing contaminants and metal oxides from the substrate surface in the integrated system, and reconditioning the substrate surface using a reducing environment after removing contaminants and metal oxides in the integrated system. The method also includes selectively depositing the thin layer of cobalt-alloy material on the copper surface of the copper interconnect in the integrated system after reconditioning the substrate surface. An exemplary system to practice the exemplary method described above is also provided.

摘要翻译： 这些实施方案通过提供改进的工艺和系统来提供改进的金属 - 金属界面，更具体地说是铜 - 金属界面，从而满足增强电迁移性能，提供较低的金属电阻率以及改善铜互连的金属 - 金属界面粘附的需要， 钴合金界面。 提供了一种制备基板的基板表面的示例性方法，以在集成系统中选择性地在基板的铜互连的铜表面上沉积钴合金材料的薄层，以改善铜互连的电迁移性能。 该方法包括从集成系统中的衬底表面去除污染物和金属氧化物，并且在去除集成系统中的污染物和金属氧化物之后，使用还原环境来修复衬底表面。 该方法还包括在修复基板表面之后，在集成系统中的铜互连的铜表面上选择性地沉积钴合金材料的薄层。 还提供了用于实践上述示例性方法的示例性系统。