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31.
公开(公告)号:US20080047137A1
公开(公告)日:2008-02-28
申请号:US11826758
申请日:2007-07-18
申请人: Toshiyuki Asahi , Seiji Karashima , Takashi Ichiryu , Seiichi Nakatani , Tousaku Nishiyama , Koichi Hirano , Osamu Shibata , Takeshi Nakayama , Yoshiyuki Saito
发明人: Toshiyuki Asahi , Seiji Karashima , Takashi Ichiryu , Seiichi Nakatani , Tousaku Nishiyama , Koichi Hirano , Osamu Shibata , Takeshi Nakayama , Yoshiyuki Saito
CPC分类号: H05K3/403 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01R12/52 , H01R13/2414 , H05K1/0218 , H05K1/0284 , H05K1/141 , H05K1/145 , H05K1/182 , H05K3/20 , H05K3/3442 , H05K3/361 , H05K3/366 , H05K3/368 , H05K2201/043 , H05K2201/048 , H05K2201/049 , H05K2201/055 , H05K2201/056 , H05K2201/09036 , H05K2201/10515 , H05K2201/10689 , H05K2203/302 , Y10T29/49117 , Y10T29/49126 , Y10T29/49208 , H01L2924/00
摘要: A connection member can be produced without a via-forming step. The connection member includes an insulating substrate which has an upper surface, a lower surface opposed to the upper surface, and a side surface which connects these surfaces; and at least one wiring which extends from the upper surface to the lower surface through the side surface.
摘要翻译: 可以在没有通孔形成步骤的情况下制造连接构件。 连接构件包括绝缘基板,其具有上表面,与上表面相对的下表面和连接这些表面的侧表面; 以及至少一个通过侧面从上表面延伸到下表面的布线。
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32.
公开(公告)号:US07258549B2
公开(公告)日:2007-08-21
申请号:US11060550
申请日:2005-02-18
申请人: Toshiyuki Asahi , Seiji Karashima , Takashi Ichiryu , Seiichi Nakatani , Tousaku Nishiyama , Koichi Hirano , Osamu Shibata , Takeshi Nakayama , Yoshiyuki Saito
发明人: Toshiyuki Asahi , Seiji Karashima , Takashi Ichiryu , Seiichi Nakatani , Tousaku Nishiyama , Koichi Hirano , Osamu Shibata , Takeshi Nakayama , Yoshiyuki Saito
IPC分类号: H01R12/00
CPC分类号: H05K3/403 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01R12/52 , H01R13/2414 , H05K1/0218 , H05K1/0284 , H05K1/141 , H05K1/145 , H05K1/182 , H05K3/20 , H05K3/3442 , H05K3/361 , H05K3/366 , H05K3/368 , H05K2201/043 , H05K2201/048 , H05K2201/049 , H05K2201/055 , H05K2201/056 , H05K2201/09036 , H05K2201/10515 , H05K2201/10689 , H05K2203/302 , Y10T29/49117 , Y10T29/49126 , Y10T29/49208 , H01L2924/00
摘要: A connection member can be produced without a via-forming step. The connection member includes an insulating substrate which has an upper surface, a lower surface opposed to the upper surface, and a side surface which connects these surfaces; and at least one wiring which extends from the upper surface to the lower surface through the side surface.
摘要翻译: 可以在没有通孔形成步骤的情况下制造连接构件。 连接构件包括绝缘基板,其具有上表面,与上表面相对的下表面和连接这些表面的侧表面; 以及至少一个通过侧面从上表面延伸到下表面的布线。
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公开(公告)号:US08343822B2
公开(公告)日:2013-01-01
申请号:US12681445
申请日:2009-07-30
CPC分类号: H01L29/78651 , H01L27/1218 , H01L27/124 , H01L27/1266 , H01L29/41733 , H01L29/42384 , H01L29/78603 , H01L29/7869
摘要: A method for manufacturing a flexible semiconductor device includes (i) forming an insulating film on the upper surface of metal foil, (ii) forming an extraction electrode pattern on the upper surface of the metal foil, (iii) forming a semiconductor layer on the insulating film such that the semiconductor layer is in contact with the extraction electrode pattern, (iv) forming a sealing resin layer on the upper surface of the metal foil such that the sealing resin layer covers the semiconductor layer and the extraction electrode pattern, and (v) forming electrodes by etching the metal foil, the metal foil being used as a support for the insulating film, the extraction electrode pattern, the semiconductor layer, and the sealing resin layer formed in (i) to (iv) and used as a constituent material for the electrodes in (v). The metal foil need not be stripped, and a high-temperature process can be used.
摘要翻译: 一种制造柔性半导体器件的方法包括:(i)在金属箔的上表面上形成绝缘膜,(ii)在金属箔的上表面上形成引出电极图案,(iii)在金属箔的上表面上形成半导体层 绝缘膜,使得半导体层与引出电极图案接触,(iv)在金属箔的上表面上形成密封树脂层,使得密封树脂层覆盖半导体层和引出电极图案,和( v)通过蚀刻金属箔形成电极,金属箔用作绝缘膜的支撑体,引出电极图案,半导体层和形成在(i)至(iv)中的密封树脂层,并用作 (v)中的电极的构成材料。 金属箔不需要剥离,可以使用高温工艺。
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34.
公开(公告)号:US08064213B2
公开(公告)日:2011-11-22
申请号:US11043123
申请日:2005-01-27
IPC分类号: H05K1/18
CPC分类号: H01L21/568 , H01L21/6835 , H01L23/49805 , H01L23/5389 , H01L24/48 , H01L25/03 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L25/165 , H01L25/50 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2225/0651 , H01L2225/06524 , H01L2225/06555 , H01L2225/06582 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2225/107 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/09701 , H01L2924/12042 , H01L2924/16152 , H01L2924/181 , H01L2924/1815 , H01L2924/19105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H05K1/0284 , H05K1/183 , H05K1/187 , H05K3/20 , H05K3/403 , H05K2203/302 , H01L2924/00 , H01L2924/00012 , H01L2224/05599 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要: A module with a built-in component is provided which can be produced without a via-forming step. The module with a built-in component 100 includes an insulating sheet substrate 10 which has an upper surface 10a, a lower surface 10b opposed to the upper surface 10b and a side surface 10c which connects these surfaces. At least one wiring 20 extends from the upper surface to the lower surface through the side surface, and an electronic component 32 is disposed within the sheet substrate.
摘要翻译: 提供具有内置部件的模块,其可以在没有通孔形成步骤的情况下制造。 具有内置部件100的模块包括绝缘片基板10,其具有上表面10a,与上表面10b相对的下表面10b和连接这些表面的侧表面10c。 至少一个布线20通过侧面从上表面延伸到下表面,并且电子部件32设置在片状基板内。
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公开(公告)号:US20110162578A1
公开(公告)日:2011-07-07
申请号:US13046151
申请日:2011-03-11
CPC分类号: H01L21/563 , B23K35/0244 , H01L21/67144 , H01L21/6835 , H01L24/11 , H01L24/12 , H01L24/16 , H01L24/75 , H01L24/83 , H01L2224/05568 , H01L2224/05573 , H01L2224/11003 , H01L2224/1131 , H01L2224/13099 , H01L2224/1319 , H01L2224/133 , H01L2224/16 , H01L2224/75 , H01L2224/83192 , H01L2224/8321 , H01L2224/83815 , H01L2224/83886 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01009 , H01L2924/01011 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01056 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/10329 , H01L2924/14 , H01L2924/18161 , H01L2924/30105 , H05K3/323 , H05K3/3436 , H05K3/3484 , H05K2201/10977 , H05K2203/1361 , Y02P70/613 , Y10T29/53178 , H01L2224/05599
摘要: [Problem] To provide a flip-chip mounting method and a bump formation method applicable to flip-chip mounting of a next generation LSI and having high productivity and high reliability.[Means for Solving Problem] A semiconductor chip 20 having a plurality of electrode terminals 12 is held to oppose a circuit board 21 having a plurality of connection terminals 11 with a given gap provided therebetween, and the semiconductor chip 20 and the circuit board 21 in this state are dipped in a dipping bath 40 containing a melted resin 14 including melted solder particles for a given period of time. In this dipping process, the melted solder particles self-assemble between the connection terminals 11 of the circuit board 21 and the electrode terminals 12 of the semiconductor chip 20, so as to form connectors 22 between these terminals. Thereafter, the semiconductor chip 20 and the circuit board 21 are taken out of the dipping bath 40, and the melted resin 14 having permeated into the gap between the semiconductor chip 20 and the circuit board 21 is cured, so as to complete a flip-chip mounting body.
摘要翻译: [问题]提供一种适用于下一代LSI的倒装安装并具有高生产率和高可靠性的倒装芯片安装方法和凸块形成方法。 解决问题的手段具有多个电极端子12的半导体芯片20被保持为具有多个连接端子11的电路板21,其间设置有给定的间隙,半导体芯片20和电路板21 将该状态浸渍在包含熔融的焊料颗粒的熔融树脂14的浸渍浴40中一段给定的时间。 在该浸渍过程中,熔融的焊料颗粒自组装在电路板21的连接端子11和半导体芯片20的电极端子12之间,从而在这些端子之间形成连接器22。 此后,半导体芯片20和电路板21从浸渍浴40中取出,并且已经渗透到半导体芯片20和电路板21之间的间隙中的熔融树脂14固化, 芯片安装体。
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公开(公告)号:US20110121298A1
公开(公告)日:2011-05-26
申请号:US13054049
申请日:2010-02-05
申请人: Takashi Ichiryu , Seiichi Nakatani , Koichi Hirano
发明人: Takashi Ichiryu , Seiichi Nakatani , Koichi Hirano
IPC分类号: H01L29/786 , H01L21/336
CPC分类号: H01L29/78603 , H01L27/1218 , H01L27/1266 , H01L29/458 , H01L29/4908 , H01L29/78681 , H01L29/7869 , H01L2224/24195 , H01L2224/32245 , H01L2224/73267 , H01L2224/82 , H01L2224/92244 , H01L2924/3511 , H01L2924/3512
摘要: A method includes the steps of preparing a multilayer film 80 formed by sequentially stacking a first metal layer 10, an inorganic insulating layer 20, a semiconductor layer 30, and a second metal layer 40; forming a source electrode 42s and a drain electrode 42d comprised of the second metal layer 40 by etching the second metal layer 40; pressure-bonding a resin layer 50 onto a surface of the multilayer film 80 provided with the source electrode 42s and the drain electrode 42d to burry the source electrode 42s and the drain electrode 42d in the resin layer 50; and forming a gate electrode 10g comprised of the first metal layer 10 by etching the first metal layer 10. The inorganic insulating layer 20g functions as a gate insulating film. The semiconductor layer 30 functions as a channel.
摘要翻译: 一种方法包括制备通过顺序堆叠第一金属层10,无机绝缘层20,半导体层30和第二金属层40而形成的多层膜80的步骤; 通过蚀刻第二金属层40形成由第二金属层40构成的源电极42s和漏电极42d; 将树脂层50压接到设置有源电极42s和漏电极42d的多层膜80的表面,以将树脂层50中的源电极42s和漏电极42d嵌入; 以及通过蚀刻第一金属层10形成由第一金属层10构成的栅极电极10g。无机绝缘层20g用作栅极绝缘膜。 半导体层30用作沟道。
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37.
公开(公告)号:US20050184381A1
公开(公告)日:2005-08-25
申请号:US11060550
申请日:2005-02-18
申请人: Toshiyuki Asahi , Seiji Karashima , Takashi Ichiryu , Seiichi Nakatani , Tousaku Nishiyama , Koichi Hirano , Osamu Shibata , Takeshi Nakayama , Yoshiyuki Saito
发明人: Toshiyuki Asahi , Seiji Karashima , Takashi Ichiryu , Seiichi Nakatani , Tousaku Nishiyama , Koichi Hirano , Osamu Shibata , Takeshi Nakayama , Yoshiyuki Saito
IPC分类号: H01R13/24 , H05K1/00 , H05K1/02 , H05K1/14 , H05K1/18 , H05K3/20 , H05K3/34 , H05K3/36 , H05K3/40 , H01R27/02 , H01L23/48 , H01R12/00 , H01R25/00 , H01R31/00 , H01R33/88 , H01R33/90 , H01R33/92 , H01R33/94
CPC分类号: H05K3/403 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01R12/52 , H01R13/2414 , H05K1/0218 , H05K1/0284 , H05K1/141 , H05K1/145 , H05K1/182 , H05K3/20 , H05K3/3442 , H05K3/361 , H05K3/366 , H05K3/368 , H05K2201/043 , H05K2201/048 , H05K2201/049 , H05K2201/055 , H05K2201/056 , H05K2201/09036 , H05K2201/10515 , H05K2201/10689 , H05K2203/302 , Y10T29/49117 , Y10T29/49126 , Y10T29/49208 , H01L2924/00
摘要: A connection member is provided which can be produced without a via-forming step. The connection member 100 includes an insulating substrate 10 which has an upper surface 10a, a lower surface 10b opposed to the upper surface 10b and a side surface 10c which connects these surfaces; at least one wiring 20 which extends from the upper surface to the lower surface through the side surface.
摘要翻译: 提供了可以在没有通孔形成步骤的情况下制造的连接构件。 连接构件100包括绝缘基板10,其具有上表面10a,与上表面10b相对的下表面10b和连接这些表面的侧表面10c; 至少一个布线20,其通过侧表面从上表面延伸到下表面。
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公开(公告)号:US08525178B2
公开(公告)日:2013-09-03
申请号:US13498700
申请日:2011-04-14
申请人: Takashi Ichiryu , Seiichi Nakatani , Koichi Hirano
发明人: Takashi Ichiryu , Seiichi Nakatani , Koichi Hirano
IPC分类号: H01L29/04
CPC分类号: H01L29/7869 , H01L27/1225 , H01L27/124 , H01L27/1262 , H01L27/1292 , H01L27/3244 , H01L29/78603 , H01L2251/5338
摘要: A flexible semiconductor device includes an insulating film on which a semiconductor element is formed. The top and bottom surfaces of the insulating film have a top wiring pattern layer and a bottom wiring pattern layer, respectively. The semiconductor element includes a semiconductor layer formed on the top surface of the insulating film, a source electrode and a drain electrode formed on the top surface of the insulating film so as to contact the semiconductor layer, and a gate electrode formed on the bottom surface of the insulating film so as to be opposite the semiconductor layer. A first thickness, which is the thickness of the insulating film facing the source electrode, the drain electrode, the top wiring pattern layer, and the bottom wiring pattern layer, is greater than a second thickness, which is the thickness of the insulating film between the gate electrode and the semiconductor layer.
摘要翻译: 柔性半导体器件包括其上形成有半导体元件的绝缘膜。 绝缘膜的顶表面和底表面分别具有顶部布线图案层和底部布线图案层。 半导体元件包括形成在绝缘膜的顶表面上的半导体层,形成在绝缘膜的顶表面上以与半导体层接触的源电极和漏电极,以及形成在底表面上的栅电极 的绝缘膜与半导体层相对。 作为与源极电极,漏极电极,顶部布线图案层和底部布线图案层相对的绝缘膜的厚度的第一厚度大于第二厚度,其是第二厚度,其是绝缘膜的厚度 栅电极和半导体层。
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公开(公告)号:US07748110B2
公开(公告)日:2010-07-06
申请号:US11826758
申请日:2007-07-18
申请人: Toshiyuki Asahi , Seiji Karashima , Takashi Ichiryu , Seiichi Nakatani , Tousaku Nishiyama , Koichi Hirano , Osamu Shibata , Takeshi Nakayama , Yoshiyuki Saito
发明人: Toshiyuki Asahi , Seiji Karashima , Takashi Ichiryu , Seiichi Nakatani , Tousaku Nishiyama , Koichi Hirano , Osamu Shibata , Takeshi Nakayama , Yoshiyuki Saito
IPC分类号: H05K3/36
CPC分类号: H05K3/403 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01R12/52 , H01R13/2414 , H05K1/0218 , H05K1/0284 , H05K1/141 , H05K1/145 , H05K1/182 , H05K3/20 , H05K3/3442 , H05K3/361 , H05K3/366 , H05K3/368 , H05K2201/043 , H05K2201/048 , H05K2201/049 , H05K2201/055 , H05K2201/056 , H05K2201/09036 , H05K2201/10515 , H05K2201/10689 , H05K2203/302 , Y10T29/49117 , Y10T29/49126 , Y10T29/49208 , H01L2924/00
摘要: A connection member can be produced without a via-forming step. The connection member includes an insulating substrate which has an upper surface, a lower surface opposed to the upper surface, and a side surface which connects these surfaces; and at least one wiring which extends from the upper surface to the lower surface through the side surface.
摘要翻译: 可以在没有通孔形成步骤的情况下制造连接构件。 连接构件包括绝缘基板,其具有上表面,与上表面相对的下表面和连接这些表面的侧表面; 以及至少一个通过侧面从上表面延伸到下表面的布线。
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公开(公告)号:US20070243664A1
公开(公告)日:2007-10-18
申请号:US11579299
申请日:2006-03-07
CPC分类号: H01L21/563 , B23K35/0244 , H01L21/67144 , H01L21/6835 , H01L24/11 , H01L24/12 , H01L24/16 , H01L24/75 , H01L24/83 , H01L2224/05568 , H01L2224/05573 , H01L2224/11003 , H01L2224/1131 , H01L2224/13099 , H01L2224/1319 , H01L2224/133 , H01L2224/16 , H01L2224/75 , H01L2224/83192 , H01L2224/8321 , H01L2224/83815 , H01L2224/83886 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01009 , H01L2924/01011 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01056 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/10329 , H01L2924/14 , H01L2924/18161 , H01L2924/30105 , H05K3/323 , H05K3/3436 , H05K3/3484 , H05K2201/10977 , H05K2203/1361 , Y02P70/613 , Y10T29/53178 , H01L2224/05599
摘要: [Problem] To provide a flip-chip mounting method and a bump formation method applicable to flip-chip mounting of a next generation LSI and having high productivity and high reliability. [Means for Solving Problem] A semiconductor chip 20 having a plurality of electrode terminals 12 is held to oppose a circuit board 21 having a plurality of connection terminals 11 with a given gap provided therebetween, and the semiconductor chip 20 and the circuit board 21 in this state are dipped in a dipping bath 40 containing a melted resin 14 including melted solder particles for a given period of time. In this dipping process, the melted solder particles self-assemble between the connection terminals 11 of the circuit board 21 and the electrode terminals 12 of the semiconductor chip 20, so as to form connectors 22 between these terminals. Thereafter, the semiconductor chip 20 and the circuit board 21 are taken out of the dipping bath 40, and the melted resin 14 having permeated into the gap between the semiconductor chip 20 and the circuit board 21 is cured, so as to complete a flip-chip mounting body.
摘要翻译: [问题]提供一种适用于下一代LSI的倒装安装并具有高生产率和高可靠性的倒装芯片安装方法和凸块形成方法。 解决问题的手段具有多个电极端子12的半导体芯片20被保持为具有多个连接端子11的电路板21,其间设置有给定的间隙,并且半导体芯片20和电路板21 将该状态浸渍在包含熔融的焊料颗粒的熔融树脂14的浸渍浴40中一段给定的时间。 在该浸渍过程中,熔融的焊料颗粒自组装在电路板21的连接端子11和半导体芯片20的电极端子12之间,从而在这些端子之间形成连接器22。 此后,半导体芯片20和电路板21从浸渍浴40中取出,并且已经渗透到半导体芯片20和电路板21之间的间隙中的熔融树脂14固化, 芯片安装体。
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