公开(公告)号：US11917838B2

公开(公告)日：2024-02-27

申请号：US17582092

申请日：2022-01-24

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

IPC分类号： H10B99/00 ,  H01L27/12 ,  H01L29/24 ,  H01L29/16 ,  G11C11/405 ,  G11C16/04 ,  H01L27/105 ,  H01L27/118 ,  H10B41/20 ,  H10B41/70 ,  H10B69/00 ,  H01L29/786 ,  H01L21/822 ,  H01L27/06 ,  H01L29/78 ,  H10B12/00

CPC分类号： H10B99/00 ,  G11C11/405 ,  G11C16/0433 ,  H01L27/105 ,  H01L27/11803 ,  H01L27/124 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/16 ,  H01L29/24 ,  H01L29/247 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/78696 ,  H10B41/20 ,  H10B41/70 ,  H10B69/00 ,  G11C2211/4016 ,  H01L21/8221 ,  H01L27/0688 ,  H01L29/7833 ,  H10B12/00

摘要： An object is to provide a semiconductor device with a novel structure. The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.

公开(公告)号：US20240021688A1

公开(公告)日：2024-01-18

申请号：US18371814

申请日：2023-09-22

申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

发明人： Akio SUZUKI ,  Shinpei MATSUDA ,  Shunpei YAMAZAKI

IPC分类号： H01L29/423 ,  H01L29/06 ,  H01L21/28 ,  H10B41/70 ,  H01L29/775 ,  H01L29/778 ,  H01L29/786 ,  H01L29/788 ,  H01L29/66

CPC分类号： H01L29/42324 ,  H01L29/0673 ,  H01L29/40114 ,  H01L29/42384 ,  H01L29/42392 ,  H10B41/70 ,  H01L29/775 ,  H01L29/7786 ,  H01L29/7869 ,  H01L29/7883 ,  H01L29/78696 ,  H01L29/66969

摘要： A transistor which is resistant to a short-channel effect is provided. The transistor includes a first conductor in a ring shape, an oxide semiconductor including a region extending through an inside of a ring of the first conductor, a first insulator between the first conductor and the oxide semiconductor, a second insulator between the first conductor and the first insulator, and a charge trap layer inside the ring of the first conductor. The charge trap layer is inside the second insulator and configured to be in a floating state.

公开(公告)号：US20230397448A1

公开(公告)日：2023-12-07

申请号：US18236000

申请日：2023-08-21

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Kiyoshi KATO

IPC分类号： H10B99/00 ,  H01L27/12 ,  H01L29/24 ,  H01L29/16 ,  G11C11/405 ,  G11C16/04 ,  H01L27/105 ,  H01L27/118 ,  H10B41/20 ,  H10B41/70 ,  H10B69/00 ,  H01L29/786

CPC分类号： H10B99/00 ,  H01L27/1207 ,  H01L29/24 ,  H01L29/16 ,  G11C11/405 ,  G11C16/0433 ,  H01L27/105 ,  H01L27/11803 ,  H01L27/1225 ,  H10B41/20 ,  H10B41/70 ,  H10B69/00 ,  H01L29/7869 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/247 ,  H01L29/78693 ,  H01L29/78696 ,  G11C2211/4016 ,  H01L21/8221

摘要： An object is to provide a semiconductor device with a novel structure. The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.

公开(公告)号：US20230307467A1

公开(公告)日：2023-09-28

申请号：US18200052

申请日：2023-05-22

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Kiyoshi KATO

IPC分类号： H01L27/12 ,  H01L21/84 ,  H01L27/118 ,  H10B10/00 ,  H10B12/00 ,  H10B41/00 ,  H10B41/30 ,  H10B41/70 ,  H01L29/786 ,  H01L29/24

CPC分类号： H01L27/1255 ,  H01L21/84 ,  H01L27/11803 ,  H01L27/1225 ,  H10B10/00 ,  H10B10/125 ,  H10B12/00 ,  H10B12/05 ,  H10B12/30 ,  H10B41/00 ,  H10B41/30 ,  H10B41/70 ,  H01L29/7869 ,  H01L29/24 ,  G11C16/0433

摘要： An object of the present invention is to provide a semiconductor device having a novel structure in which in a data storing time, stored data can be stored even when power is not supplied, and there is no limitation on the number of writing. A semiconductor device includes a first transistor including a first source electrode and a first drain electrode; a first channel formation region for which an oxide semiconductor material is used and to which the first source electrode and the first drain electrode are electrically connected; a first gate insulating layer over the first channel formation region; and a first gate electrode over the first gate insulating layer. One of the first source electrode and the first drain electrode of the first transistor and one electrode of a capacitor are electrically connected to each other.

公开(公告)号：US12101945B2

公开(公告)日：2024-09-24

申请号：US18225186

申请日：2023-07-24

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Tomoaki Atsumi ,  Shuhei Nagatsuka ,  Tamae Moriwaka ,  Yuta Endo

IPC分类号： H10B69/00 ,  G11C7/16 ,  G11C8/14 ,  G11C11/24 ,  G11C11/403 ,  G11C11/408 ,  H01L27/06 ,  H01L29/24 ,  H01L29/786 ,  H10B41/20 ,  H10B41/70

CPC分类号： H10B69/00 ,  G11C7/16 ,  G11C8/14 ,  G11C11/24 ,  G11C11/403 ,  G11C11/4085 ,  H01L27/0688 ,  H01L29/24 ,  H01L29/7869 ,  H10B41/20 ,  H10B41/70

摘要： [Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed.
[Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j≥2, the jth sub memory cell is arranged over the j−1th sub memory cell.

公开(公告)号：US20240296881A1

公开(公告)日：2024-09-05

申请号：US18646415

申请日：2024-04-25

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Tomoaki ATSUMI ,  Junpei SUGAO

IPC分类号： G11C11/4094 ,  G11C11/401 ,  G11C11/4096 ,  G11C11/4097 ,  H01L27/12 ,  H01L29/786 ,  H10B10/00 ,  H10B41/70

CPC分类号： G11C11/4094 ,  G11C11/401 ,  G11C11/4096 ,  G11C11/4097 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1251 ,  H01L27/1255 ,  H01L29/78675 ,  H01L29/7869 ,  H01L29/78696 ,  H10B10/12 ,  H10B41/70

摘要： The semiconductor device includes a first memory cell, and a second memory cell thereover. The first memory cell includes first and second transistors, and a first capacitor. The second memory cell includes third and fourth transistors, and a second capacitor. A gate of the first transistor is electrically connected to one of a source and a drain of the second transistor and the first capacitor. A gate of the third transistor is electrically connected to one of a source and a drain of the fourth transistor and the second capacitor. One of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the third transistor. The second and fourth transistors include an oxide semiconductor. A channel length direction of the first and third transistors is substantially perpendicular to a channel length direction of the second and fourth transistors.

公开(公告)号：US20240234423A9

公开(公告)日：2024-07-11

申请号：US18538009

申请日：2023-12-13

申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

发明人： Shunpei YAMAZAKI

IPC分类号： H01L27/105 ,  G11C11/405 ,  G11C16/04 ,  H01L21/02 ,  H01L21/46 ,  H01L21/8258 ,  H01L27/12 ,  H01L29/06 ,  H01L29/786 ,  H10B41/10 ,  H10B41/20 ,  H10B41/30 ,  H10B41/35 ,  H10B41/70

CPC分类号： H01L27/105 ,  G11C11/405 ,  G11C16/0433 ,  H01L21/02664 ,  H01L21/46 ,  H01L21/8258 ,  H01L27/1225 ,  H01L29/06 ,  H01L29/7869 ,  H01L29/78693 ,  H10B41/10 ,  H10B41/20 ,  H10B41/30 ,  H10B41/35 ,  H10B41/70 ,  H01L27/0207

摘要： Disclosed is a semiconductor device capable of functioning as a memory device. The memory device comprises a plurality of memory cells, and each of the memory cells contains a first transistor and a second transistor. The first transistor is provided over a substrate containing a semiconductor material and has a channel formation region in the substrate. The second transistor has an oxide semiconductor layer. The gate electrode of the first transistor and one of the source and drain electrodes of the second transistor are electrically connected to each other. The extremely low off current of the second transistor allows the data stored in the memory cell to be retained for a significantly long time even in the absence of supply of electric power.

公开(公告)号：US11923372B2

公开(公告)日：2024-03-05

申请号：US17308116

申请日：2021-05-05

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Shunpei Yamazaki ,  Kensuke Yoshizumi

IPC分类号： H01L27/12 ,  H01L27/04 ,  H01L27/06 ,  H01L29/423 ,  H10B12/00 ,  H10B41/70 ,  G11C16/10 ,  H01L21/84 ,  H01L29/24 ,  H10B41/20 ,  H10B41/30

CPC分类号： H01L27/1207 ,  H01L27/04 ,  H01L27/0688 ,  H01L29/42384 ,  H10B12/00 ,  H10B41/70 ,  G11C16/10 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/24 ,  H10B12/30 ,  H10B41/20 ,  H10B41/30

摘要： A semiconductor device is described, which includes a first transistor, a second transistor, and a capacitor. The second transistor and the capacitor are provided over the first transistor so as to overlap with a gate of the first transistor. A semiconductor layer of the second transistor and a dielectric layer of the capacitor are directly connected to the gate of the first transistor. The second transistor is a vertical transistor, where its channel direction is perpendicular to an upper surface of a semiconductor layer of the first transistor.

公开(公告)号：US11894380B2

公开(公告)日：2024-02-06

申请号：US16691730

申请日：2019-11-22

申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

发明人： Shunpei Yamazaki

IPC分类号： H01L27/105 ,  H01L29/06 ,  H01L29/786 ,  H01L21/02 ,  H01L21/46 ,  H01L27/12 ,  G11C11/405 ,  G11C16/04 ,  H01L21/8258 ,  H10B41/10 ,  H10B41/20 ,  H10B41/30 ,  H10B41/35 ,  H10B41/70 ,  H01L29/78 ,  H01L49/02 ,  H01L27/02

CPC分类号： H01L27/105 ,  G11C11/405 ,  G11C16/0433 ,  H01L21/02664 ,  H01L21/46 ,  H01L21/8258 ,  H01L27/1225 ,  H01L29/06 ,  H01L29/7869 ,  H01L29/78693 ,  H10B41/10 ,  H10B41/20 ,  H10B41/30 ,  H10B41/35 ,  H10B41/70 ,  H01L27/0207 ,  H01L28/60 ,  H01L29/7833

摘要： Disclosed is a semiconductor device capable of functioning as a memory device. The memory device comprises a plurality of memory cells, and each of the memory cells contains a first transistor and a second transistor. The first transistor is provided over a substrate containing a semiconductor material and has a channel formation region in the substrate. The second transistor has an oxide semiconductor layer. The gate electrode of the first transistor and one of the source and drain electrodes of the second transistor are electrically connected to each other. The extremely low off current of the second transistor allows the data stored in the memory cell to be retained for a significantly long time even in the absence of supply of electric power.

公开(公告)号：US20230413549A1

公开(公告)日：2023-12-21

申请号：US18080963

申请日：2022-12-14

申请人： Kioxia Corporation

发明人： Yuta TSUCHIYA

IPC分类号： H10B43/20 ,  H01L27/02 ,  H10B41/47 ,  H10B41/70 ,  H10B43/35 ,  H01L27/12

CPC分类号： H10B43/20 ,  H01L27/0207 ,  H01L27/12 ,  H10B41/70 ,  H10B43/35 ,  H10B41/47

摘要： A semiconductor memory device includes finger structures arranged in a first direction, a bit line disposed on one side in a stacking direction with respect to the finger structures, and an inter-finger insulating layer disposed between two finger structures. A first finger structure includes conductive layers, a semiconductor layer opposed to the conductive layers, a first insulating layer disposed between the bit line and the conductive layers, and a second insulating layer disposed between the first insulating layer and the conductive layers. A distance between the first insulating layer and the inter-finger insulating layer at a position corresponding to a surface on a side of the bit line of the first insulating layer is larger than a distance between the second insulating layer and the inter-finger insulating layer at a position corresponding to a surface on an opposite side of the bit line of the second insulating layer.