公开(公告)号：US08937505B2

公开(公告)日：2015-01-20

申请号：US14134081

申请日：2013-12-19

Applicant: Commissariat à l'énergie atomique et aux énergies alternatives ,  STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Bastien Giraud ,  Fady Abouzeid ,  Sylvain Clerc ,  Jean-Philippe Noel ,  Yvain Thonnart

IPC: H03K3/01 ,  G05F3/02 ,  H01L21/84 ,  H01L27/118 ,  H01L27/12 ,  H03K19/177 ,  H01L29/786

CPC classification number: G05F3/02 ,  H01L21/84 ,  H01L27/11807 ,  H01L27/1203 ,  H01L29/78648 ,  H03K19/1774

Abstract: The invention relates to an integrated circuit comprising: a first semiconductor well (60); a plurality of standard cells (66), each standard cell comprising a first field-effect transistor in FDSOI technology comprising a first semiconductor ground plane located immediately on the first well; and a clock tree cell (30) contiguous with the standard cells, the clock tree cell comprising a second field-effect transistor in FDSOI technology, which transistor comprises a second semiconductor ground plane located immediately on the first well (60), so as to form a p-n junction with this first well. The integrated circuit comprises an electrical power supply network (51) able to apply separate electrical biases directly to the first and second ground planes.

Abstract translation: 本发明涉及一种集成电路，包括：第一半导体阱（60）; 多个标准单元（66），每个标准单元包括FDSOI技术中的第一场效应晶体管，其包括位于第一阱上的第一半导体接地平面; 以及与所述标准单元相邻的时钟树单元（30），所述时钟树单元包括FDSOI技术中的第二场效应晶体管，所述晶体管包括位于所述第一阱（60）上的第二半导体接地平面，以便 与第一口井形成一个pn结。 集成电路包括能够将分离的电偏压直接施加到第一和第二接地层的电力供应网络（51）。

公开(公告)号：US20140376857A1

公开(公告)日：2014-12-25

申请号：US14311496

申请日：2014-06-23

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Alain Chantre ,  Sébastien Cremer

IPC: G02B6/122

CPC classification number: G02B6/12002 ,  G02B6/12004 ,  H01S5/021 ,  H01S5/026 ,  H01S5/0262 ,  H01S5/0422 ,  H01S5/1032 ,  H01S5/34306 ,  H01S2301/176

Abstract: A photonic integrated circuit may include a silicon layer including a waveguide and at least one other photonic component. The photonic integrated circuit may also include a first insulating region arranged above a first side of the silicon layer and encapsulating at least one metallization level, a second insulating region arranged above a second side of the silicon layer and encapsulating at least one gain medium of a laser source optically coupled to the waveguide.

Abstract translation: 光子集成电路可以包括包括波导和至少一个其它光子分量的硅层。 光子集成电路还可以包括布置在硅层的第一侧上方并封装至少一个金属化层的第一绝缘区域，布置在硅层的第二侧上方的第二绝缘区域，并封装至少一个增强介质 激光源光耦合到波导。

公开(公告)号：US20140370666A1

公开(公告)日：2014-12-18

申请号：US14177593

申请日：2014-02-11

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT ,  STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Maud VINET ,  Yves Morand ,  Heimanu Niebojewski

IPC: H01L29/66 ,  H01L21/762 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/306

CPC classification number: H01L29/66477 ,  H01L21/02236 ,  H01L21/02667 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/7624 ,  H01L21/76248 ,  H01L21/76272 ,  H01L21/76278 ,  H01L21/84 ,  H01L27/1207

Abstract: A method is provided for producing a semiconductor layer having at least two different thicknesses from a stack of the semiconductor on insulator type including at least one substrate on which an insulating layer and a first semiconductor layer are successively disposed, the method including etching the first layer so that said layer is continuous and includes at least one first region having a thickness less than that of at least one second region; oxidizing the first layer to form an electrically insulating oxide film on a surface thereof so that, in the first region, the oxide film extends as far as the insulating layer; partly removing the oxide film to bare the first layer outside the first region; forming a second semiconductor layer on the stack, to form, with the first layer, a third continuous semiconductor layer having a different thickness than that of the first and second regions.

Abstract translation: 提供一种用于制造半导体层的半导体层的方法，所述半导体层具有至少两个不同厚度的绝缘体上的半导体层，包括至少一个其上连续设置有绝缘层和第一半导体层的基板，所述方法包括蚀刻第一层 使得所述层是连续的并且包括至少一个具有小于至少一个第二区域的厚度的第一区域; 氧化第一层以在其表面上形成电绝缘氧化膜，使得在第一区域中，氧化膜延伸至绝缘层; 部分地除去氧化膜以露出第一区域外的第一层; 在所述堆叠上形成第二半导体层，以与所述第一层形成具有与所述第一和第二区域的厚度不同的厚度的第三连续半导体层。

公开(公告)号：US08907481B2

公开(公告)日：2014-12-09

申请号：US13869072

申请日：2013-04-24

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Laurent-Luc Chapelon

IPC: H01L23/48 ,  H01L21/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065 ,  H01L21/683 ,  H01L21/56

CPC classification number: H01L23/5384 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/7682 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/5386 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/80 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05647 ,  H01L2224/11912 ,  H01L2224/13005 ,  H01L2224/13007 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16237 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/80141 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/81141 ,  H01L2224/81815 ,  H01L2224/9201 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/2064 ,  H01L2924/20754 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2224/11 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A stack of a first and second semiconductor structures is formed. Each semiconductor structure includes: a semiconductor bulk, an overlying insulating layer with metal interconnection levels, and a first surface including a conductive area. The first surfaces of semiconductor structures face each other. A first interconnection pillar extends from the first surface of the first semiconductor structure. A housing opens into the first surface of the second semiconductor structure. The housing is configured to receive the first interconnection pillar. A second interconnection pillar protrudes from a second surface of the second semiconductor structure which is opposite the first surface. The second interconnection pillar is in electric contact with the first interconnection pillar.

Abstract translation: 形成第一和第二半导体结构的堆叠。 每个半导体结构包括：半导体本体，具有金属互连电平的上覆绝缘层，以及包括导电区域的第一表面。 半导体结构的第一表面彼此面对。 第一互连柱从第一半导体结构的第一表面延伸。 外壳通向第二半导体结构的第一表面。 壳体被配置为接收第一互连支柱。 第二互连柱从与第一表面相对的第二半导体结构的第二表面突出。 第二互连柱与第一互连柱电接触。

公开(公告)号：US08895420B2

公开(公告)日：2014-11-25

申请号：US14040270

申请日：2013-09-27

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Daniel-Camille Bensahel ,  Yves Morand

IPC: H01L29/36 ,  H01L21/22 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/306 ,  H01L29/66

CPC classification number: H01L21/22 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/02664 ,  H01L21/30604 ,  H01L21/3065 ,  H01L29/36 ,  H01L29/66659

Abstract: A semiconductive device is fabricated by forming, within a semiconductive substrate, at least one continuous region formed of a material having a non-uniform composition in a direction substantially perpendicular to the thickness of the substrate.

Abstract translation: 半导体器件通过在半导体衬底内形成至少一个由具有基本上垂直于衬底厚度的方向上具有不均匀组成的材料形成的连续区域来制造。

公开(公告)号：US20140340133A1

公开(公告)日：2014-11-20

申请号：US14276567

申请日：2014-05-13

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics Pvt. Ltd.

Inventor： Gilles Gasiot ,  Sylvain Clerc ,  Junaid Yousuf ,  Maximilien Glorieux

IPC: H03K19/003 ,  H03L7/08

CPC classification number: H03K19/0033 ,  G11C5/005 ,  H03K3/0375 ,  H03K3/356121 ,  H03L7/08 ,  H03L7/0891 ,  H03L7/0896 ,  H03L7/095 ,  H03L7/18

Abstract: A circuit including a data storage element; first and second input circuitry coupled respectively to first and second inputs of the data storage element and each including a plurality of components adapted to generate, as a function of an initial signal, first and second input signals respectively provided to the first and second inputs; wherein the data storage element includes a first storage node and is configured such that a voltage state stored at the first storage node is protected from a change in only one of the first and second input signals by being determined by the conduction state of a first transistor coupled to the first storage node and controlled based on the first input signal and by the conduction state of a second transistor coupled to the first storage node and controlled based on the second input signal.

Abstract translation: 一种包括数据存储元件的电路; 第一和第二输入电路分别耦合到数据存储元件的第一和第二输入端，并且每个输入电路包括适于产生分别提供给第一和第二输入的第一和第二输入信号作为初始信号的函数的多个分量; 其中所述数据存储元件包括第一存储节点，并且被配置为使得通过由第一晶体管的导通状态来确定存储在所述第一存储节点处的电压状态以防止所述第一和第二输入信号中仅一个的变化 耦合到所述第一存储节点并且基于所述第一输入信号以及耦合到所述第一存储节点的第二晶体管的导通状态并基于所述第二输入信号进行控制。

公开(公告)号：US20140335663A1

公开(公告)日：2014-11-13

申请号：US14177614

申请日：2014-02-11

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT ,  STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Heimanu NIEBOJEWSKI ,  Yves Morand ,  Maud Vinet

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78603

Abstract: A method for manufacturing a transistor includes forming a stack of semiconductor on insulator type layers including at least one substrate, surmounted by a first insulating layer and an active layer to form a channel for the transistor; forming a gate stack on the active layer; producing a source and a drain including forming, on either side of the gate stack, cavities by at least one step of etching the active layer, the first insulating layer, and part of the substrate selectively to the gate stack to remove the active layer, the first insulating layer, and a portion of the substrate outside regions situated below the gate stack; forming a second insulating layer on the bared surfaces of the substrate, to form a continuous insulating layer with the first insulating layer; baring of the lateral ends of the channel; and the filling of the cavities by epitaxy.

Abstract translation: 一种制造晶体管的方法，包括：形成绝缘体上半导体层的叠层，其包括至少一个衬底，其被第一绝缘层和有源层所覆盖以形成晶体管的沟道; 在有源层上形成栅叠层; 产生源极和漏极，包括在栅叠层的任一侧通过至少一个步骤，至少一个步骤，将有源层，第一绝缘层和衬底的一部分选择性地栅极堆叠以形成去除有源层， 所述第一绝缘层和位于所述栅叠层下方的所述衬底外部区域的一部分; 在所述基板的裸露表面上形成第二绝缘层，以形成具有所述第一绝缘层的连续绝缘层; 通道的横向端部露出; 并通过外延填充空腔。

公开(公告)号：US08877600B2

公开(公告)日：2014-11-04

申请号：US14104903

申请日：2013-12-12

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics S.A. ,  STMicroelectronics, Inc. ,  Commissariat à l'Énergie Atomique et aux Énergies Alternatives

Inventor： Claire Fenouillet-Beranger ,  Stephane Denorme ,  Nicolas Loubet ,  Qing Liu ,  Emmanuel Richard ,  Pierre Perreau

IPC: H01L21/20 ,  H01L21/762

CPC classification number: H01L21/76283 ,  H01L21/84 ,  H01L27/1207

Abstract: A method for manufacturing a hybrid SOI/bulk substrate, including the steps of starting from an SOI wafer comprising a single-crystal semiconductor layer called SOI layer, on an insulating layer, on a single-crystal semiconductor substrate; depositing on the SOI layer at least one masking layer and forming openings crossing the masking layer, the SOI layer, and the insulating layer, to reach the substrate; growing by a repeated alternation of selective epitaxy and partial etching steps a semiconductor material; and etching insulating trenches surrounding said openings filled with semiconductor material, while encroaching inwards over the periphery of the openings.

Abstract translation: 一种制造混合SOI /体基板的方法，包括以下步骤：在绝缘层上在单晶半导体衬底上从包括称为SOI层的单晶半导体层的SOI晶片开始; 在SOI层上沉积至少一个掩模层，并形成与掩模层，SOI层和绝缘层交叉的开口，以到达衬底; 通过选择性外延和部分蚀刻步骤的重复交替生长半导体材料; 以及蚀刻围绕填充有半导体材料的所述开口的绝缘沟槽，同时在开口的周边向内侵入。

公开(公告)号：US20140283367A1

公开(公告)日：2014-09-25

申请号：US14221402

申请日：2014-03-21

Applicant: STMICROELECTRONICS (CROLLES 2) SAS ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT

Inventor： Jean Berthier ,  Lea Di Cioccio ,  Sebastien Mermoz

IPC: B23Q3/02

CPC classification number: B23Q3/02 ,  H01L23/49838 ,  H01L25/50 ,  H01L2224/26175 ,  H01L2224/95146 ,  H01L2924/0002 ,  Y10T29/49982 ,  Y10T29/49998 ,  Y10T29/53091 ,  Y10T29/53178 ,  H01L2924/00

Abstract: Support comprising a reception zone in which the external envelope matches the shape of a plate (P2) designed to be placed on a droplet deposited at least in the reception zone in order to achieve capillary self-assembly of the plate and the support, and at least one pair of tracks (T11, T12) that extend on the support from the reception zone and that have a lyophilic type affinity with the droplet such that an overflow of the droplet beyond the reception zone is guided in the tracks, characterised in that the at least one pair of tracks comprises a first track (T11) and a second track (T12) that do not have the same lyophilic type degree of affinity with the droplet.

Abstract translation: 支撑件包括接收区域，其中外部封套匹配设计成放置在至少在接收区域中沉积的液滴上的板（P2）的形状，以便实现板和支撑件的毛细管自组装，并且在 至少一对轨道（T11，T12），其在所述支撑体上从所述接收区域延伸并且具有与所述液滴的亲液亲和性，使得所述液滴超过所述接收区域的溢出被引导到所述轨道中，其特征在于， 至少一对轨迹包括与液滴不具有相同亲液性亲和度的第一轨道（T11）和第二轨道（T12）。

公开(公告)号：US20140183778A1

公开(公告)日：2014-07-03

申请号：US14108940

申请日：2013-12-17

Applicant: STMICROELECTRONICS (CROLLES 2) SAS ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT

Inventor： Jean-Philippe COLONNA ,  Christophe AUMONT ,  Stefan LANDIS

IPC: H01H1/00

CPC classification number: H01H1/00 ,  H01L21/76817 ,  H01L23/3157 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02372 ,  H01L2224/0346 ,  H01L2224/0348 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/05548 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/10126 ,  H01L2224/13008 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13028 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14505 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2224/05552

Abstract: A method for making a conducting structure comprising steps of: forming on a given face of the support comprising at least one conducting element, at least one area for absorbing stresses based on a dielectric material, forming at least one aperture in said dielectric material by applying a mold on said dielectric material, said aperture being provided with inclined walls relatively to a normal to the main plane of said support, the bottom of said aperture revealing said conducting element, filling said aperture with a conducting material.

Abstract translation: 一种用于制造导电结构的方法，包括以下步骤：在包括至少一个导电元件的支撑体的给定面上形成至少一个用于吸收基于电介质材料的应力的区域，通过施加在所述电介质材料中形成至少一个孔 在所述电介质材料上的模具，所述孔相对于所述支撑件的主平面的法线设置有倾斜壁，所述孔的底部露出所述导电元件，用导电材料填充所述孔。