公开(公告)号：US20100203731A1

公开(公告)日：2010-08-12

申请号：US12368110

申请日：2009-02-09

Applicant: Bob Kong ,  Zhi-Wen Sun ,  Chi-I Lang ,  Jinhong Tong ,  Tony Chiang

Inventor： Bob Kong ,  Zhi-Wen Sun ,  Chi-I Lang ,  Jinhong Tong ,  Tony Chiang

IPC: H01L21/306 ,  C09D1/00 ,  H01L21/34

CPC classification number: H01L21/02068 ,  C23C18/1651 ,  C23C18/54 ,  H01L21/288 ,  H01L21/76852 ,  H01L21/76874

Abstract: Embodiments of the current invention describe methods of processing a semiconductor substrate that include applying a zincating solution to the semiconductor substrate to form a zinc passivation layer on the titanium-containing layer, the zincating solution comprising a zinc salt, FeCl3, and a pH adjuster.

Abstract translation: 本发明的实施方案描述了处理半导体衬底的方法，其包括将锌化溶液施加到半导体衬底上以在含钛层上形成锌钝化层，所述锌化溶液包含锌盐FeCl 3和pH调节剂。

公开(公告)号：US07727906B1

公开(公告)日：2010-06-01

申请号：US11493679

申请日：2006-07-26

Applicant: Sunil Shanker ,  Chi-I Lang ,  Minh Anh Nguyen ,  Judy H. Huang

Inventor： Sunil Shanker ,  Chi-I Lang ,  Minh Anh Nguyen ,  Judy H. Huang

IPC: H01L21/31

CPC classification number: C23C16/045 ,  C23C16/4404 ,  C23C16/4405 ,  H01J37/32165 ,  H01L21/31604

Abstract: This invention relates to electronic device fabrication for making devices such as semiconductor wafers and resolves the detrimental fluorine loading effect on deposition in the reaction chamber of a HDP CVD apparatus used for forming dielectric layers in high aspect ratio, narrow width recessed features with a repeating dep/etch/dep process. The detrimental fluorine loading effect in the chamber on deposition uniformity is reduced and wafers are provided having less deposition thickness variations by employing the method using a passivation treatment and precoating of the chamber before substrates are processed. In a preferred process, after each wafer of a batch is finished, the passivation steps are repeated. In a further preferred process, after all the wafers of a batch are finished, the passivation and precoat procedure is repeated. A preferred passivation gas is a mixture of hydrogen and oxygen.

Abstract translation: 本发明涉及用于制造诸如半导体晶片的器件的电子器件制造，并且解决了用于形成具有高纵横比，窄宽度凹陷特征的电介质层的HDP CVD设备的反应室中沉积的有害氟负载效应，具有重复的dep / etch / dep进程。 通过采用钝化处理的方法和在处理基板之前对涂层进行涂布，在沉积均匀性方面降低了室中对有害的氟负载效应并提供具有较小沉积厚度变化的晶片。 在优选的方法中，在批次的每个晶片完成之后，重复钝化步骤。 在另一优选方法中，在批料的所有晶片完成之后，重复钝化和预涂步骤。 优选的钝化气体是氢和氧的混合物。

公开(公告)号：US07704789B2

公开(公告)日：2010-04-27

申请号：US11702967

申请日：2007-02-05

Applicant: Zhi-wen Sun ,  Nitin Kumar ,  Jinhong Tong ,  Chi-I Lang ,  Tony Chiang

Inventor： Zhi-wen Sun ,  Nitin Kumar ,  Jinhong Tong ,  Chi-I Lang ,  Tony Chiang

IPC: H01L21/00

CPC classification number: H01L45/04 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1633

Abstract: Resistive switching memory elements are provided that may contain electroless metal electrodes and metal oxides formed from electroless metal. The resistive switching memory elements may exhibit bistability and may be used in high-density multi-layer memory integrated circuits. Electroless conductive materials such as nickel-based materials may be selectively deposited on a conductor on a silicon wafer or other suitable substrate. The electroless conductive materials can be oxidized to form a metal oxide for a resistive switching memory element. Multiple layers of conductive materials can be deposited each of which has a different oxidation rate. The differential oxidization rates of the conductive layers can be exploited to ensure that metal oxide layers of desired thicknesses are formed during fabrication.

Abstract translation: 提供电阻式开关存储器元件，其可以包含由无电金属形成的化学金属电极和金属氧化物。 电阻式开关存储器元件可以表现出双稳态，并且可以用于高密度多层存储器集成电路中。 诸如镍基材料的无电导电材料可以选择性地沉积在硅晶片或其它合适的衬底上的导体上。 无电导电材料可以被氧化以形成用于电阻式开关存储元件的金属氧化物。 可以沉积多层导电材料，每层具有不同的氧化速率。 可以利用导电层的差异氧化速率来确保在制造期间形成所需厚度的金属氧化物层。

公开(公告)号：US20090014846A1

公开(公告)日：2009-01-15

申请号：US12172110

申请日：2008-07-11

Applicant: Zachary M. Fresco ,  Chi-I Lang ,  Jinhong Tong ,  Anh Duong ,  Nitin Kumar ,  Anna Tsimelzon ,  Tony Chiang

Inventor： Zachary M. Fresco ,  Chi-I Lang ,  Jinhong Tong ,  Anh Duong ,  Nitin Kumar ,  Anna Tsimelzon ,  Tony Chiang

IPC: H01L21/312 ,  H01L29/51

CPC classification number: H01L23/5329 ,  C09D129/04 ,  H01L21/02063 ,  H01L21/02074 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76829 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of modifying a patterned semiconductor substrate are presented including: providing a patterned semiconductor substrate surface including a dielectric region and a conductive region; and applying an amphiphilic surface modifier to the dielectric region to modify the dielectric region. In some embodiments, modifying the dielectric region includes modifying a wetting angle of the dielectric region. In some embodiments, modifying the wetting angle includes making a surface of the dielectric region hydrophilic. In some embodiments, methods further include applying an aqueous solution to the patterned semiconductor substrate surface. In some embodiments, the conductive region is selectively enhanced by the aqueous solution. In some embodiments, methods further include providing the dielectric region formed of a low-k dielectric material. In some embodiments, applying the amphiphilic surface modifier modifies an interaction of the low-k dielectric region with a subsequent process.

Abstract translation: 提出了修改图案化半导体衬底的方法，包括：提供包括电介质区域和导电区域的图案化半导体衬底表面; 以及将两亲表面改性剂施加到所述电介质区域以改变所述电介质区域。 在一些实施例中，修改电介质区域包括改变电介质区域的润湿角度。 在一些实施例中，改变润湿角度包括使介电区域的表面成为亲水性。 在一些实施方案中，方法还包括将水溶液施加到图案化的半导体衬底表面。 在一些实施例中，导电区域被水溶液选择性地增强。 在一些实施例中，方法还包括提供由低k电介质材料形成的电介质区域。 在一些实施方案中，施加两亲表面改性剂修饰低k电介质区域与随后工艺的相互作用。

公开(公告)号：US07465659B2

公开(公告)日：2008-12-16

申请号：US11426141

申请日：2006-06-23

Applicant: Kang Sub Yim ,  Melissa M. Tam ,  Dian Sugiarto ,  Chi-I Lang ,  Peter Wai-Man Lee ,  Li-Qun Xia

Inventor： Kang Sub Yim ,  Melissa M. Tam ,  Dian Sugiarto ,  Chi-I Lang ,  Peter Wai-Man Lee ,  Li-Qun Xia

IPC: H01L21/4763

CPC classification number: H01L21/76834 ,  C23C16/30 ,  C23C16/325 ,  C23C16/401 ,  C23C16/505 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/312 ,  H01L21/3122 ,  H01L21/3127 ,  H01L21/3148 ,  H01L21/31633 ,  H01L21/3185 ,  H01L21/76807 ,  H01L21/7681 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832

Abstract: Methods are provided for depositing a silicon carbide layer having significantly reduced current leakage. The silicon carbide layer may be a barrier layer or part of a barrier bilayer that also includes a barrier layer. Methods for depositing oxygen-doped silicon carbide barrier layers are also provided. The silicon carbide layer may be deposited by reacting a gas mixture comprising an organosilicon compound, an aliphatic hydrocarbon comprising a carbon-carbon double bond or a carbon-carbon triple bond, and optionally, helium in a plasma. Alternatively, the silicon carbide layer may be deposited by reacting a gas mixture comprising hydrogen or argon and an organosilicon compound in a plasma.

Abstract translation: 提供了用于沉积具有显着降低的电流泄漏的碳化硅层的方法。 碳化硅层可以是还包括阻挡层的阻挡层或阻挡层双层的一部分。 还提供了沉积氧掺杂的碳化硅阻挡层的方法。 可以通过使包含有机硅化合物，包含碳 - 碳双键或碳 - 碳三键的脂族烃和任选地在等离子体中的氦气的气体混合物反应来沉积碳化硅层。 或者，可以通过在等离子体中使包含氢或氩的气体混合物和有机硅化合物反应来沉积碳化硅层。

公开(公告)号：US20080219039A1

公开(公告)日：2008-09-11

申请号：US11714326

申请日：2007-03-05

Applicant: Nitin Kumar ,  Jinhong Tong ,  Chi-I Lang ,  Prashant B. Phatak

Inventor： Nitin Kumar ,  Jinhong Tong ,  Chi-I Lang ,  Prashant B. Phatak

IPC: G11C11/00

CPC classification number: G11C13/0007 ,  G11C2213/32 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1608

Abstract: Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed by depositing a metal-containing material on a silicon-containing material. The metal-containing material may be oxidized to form a resistive-switching metal oxide. The silicon in the silicon-containing material reacts with the metal in the metal-containing material when heat is applied. This forms a metal silicide lower electrode for the nonvolatile memory element. An upper electrode may be deposited on top of the metal oxide. Because the silicon in the silicon-containing layer reacts with some of the metal in the metal-containing layer, the resistive-switching metal oxide that is formed is metal deficient when compared to a stoichiometric metal oxide formed from the same metal.

Abstract translation: 提供具有电阻开关金属氧化物的非易失性存储元件。 非易失性存储元件可以通过将含金属的材料沉积在含硅材料上而形成。 含金属材料可以被氧化以形成电阻式开关金属氧化物。 当施加热量时，含硅材料中的硅与含金属材料中的金属反应。 这形成用于非易失性存储元件的金属硅化物下电极。 上部电极可以沉积在金属氧化物的顶部。 由于含硅层中的硅与含金属层中的一些金属反应，与由相同金属形成的化学计量的金属氧化物相比，形成的电阻 - 开关金属氧化物是金属缺陷的。

公开(公告)号：US06838393B2

公开(公告)日：2005-01-04

申请号：US10247404

申请日：2002-09-19

Applicant: Kang Sub Yim ,  Melissa M. Tam ,  Dian Sugiarto ,  Chi-I Lang ,  Peter Wai-Man Lee ,  Li-Qun Xia

Inventor： Kang Sub Yim ,  Melissa M. Tam ,  Dian Sugiarto ,  Chi-I Lang ,  Peter Wai-Man Lee ,  Li-Qun Xia

IPC: C23C16/30 ,  C23C16/40 ,  C23C16/56 ,  H01L21/311 ,  H01L21/312 ,  H01L21/316 ,  H01L21/768 ,  H01L21/469 ,  H01L21/31

CPC classification number: H01L21/76834 ,  C23C16/30 ,  C23C16/325 ,  C23C16/401 ,  C23C16/505 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/312 ,  H01L21/3122 ,  H01L21/3127 ,  H01L21/3148 ,  H01L21/31633 ,  H01L21/3185 ,  H01L21/76807 ,  H01L21/7681 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832

Abstract: Methods are provided for depositing a silicon carbide layer having significantly reduced current leakage. The silicon carbide layer may be a barrier layer or part of a barrier bilayer that also includes a barrier layer. Methods for depositing oxygen-doped silicon carbide barrier layers are also provided. The silicon carbide layer may be deposited by reacting a gas mixture comprising an organosilicon compound, an aliphatic hydrocarbon comprising a carbon-carbon double bond or a carbon-carbon triple bond, and optionally, helium in a plasma. Alternatively, the silicon carbide layer may be deposited by reacting a gas mixture comprising hydrogen or argon and an organosilicon compound in a plasma.

Abstract translation: 提供了用于沉积具有显着降低的电流泄漏的碳化硅层的方法。 碳化硅层可以是还包括阻挡层的阻挡层或阻挡层双层的一部分。 还提供了沉积氧掺杂的碳化硅阻挡层的方法。 可以通过使包含有机硅化合物，包含碳 - 碳双键或碳 - 碳三键的脂族烃和任选地在等离子体中的氦气的气体混合物反应来沉积碳化硅层。 或者，可以通过在等离子体中使包含氢或氩的气体混合物和有机硅化合物反应来沉积碳化硅层。

公开(公告)号：US08920618B2

公开(公告)日：2014-12-30

申请号：US13339648

申请日：2011-12-29

Applicant: Hong Sheng Yang ,  Zhendong Hong ,  Chi-I Lang

Inventor： Hong Sheng Yang ,  Zhendong Hong ,  Chi-I Lang

IPC: C23C14/54

CPC classification number: C23C14/044 ,  C23C14/3464

Abstract: Apparatuses and methods for high-deposition-rate sputtering for depositing layers onto a substrate are disclosed. The apparatuses generally comprise a process chamber; one or more sputtering sources disposed within the process chamber, wherein each sputtering source comprises a sputtering target; a substrate support disposed within the process chamber; a shield positioned between the sputtering sources and the substrate, the shield comprising an aperture positioned under each sputtering source; and a transport system connected to the substrate support capable of positioning the substrate such that one of a plurality of site-isolated regions on the substrate can be exposed to sputtered material through the aperture positioned under each of the sputtering sources; wherein the spacing between the sputtering target and the substrate is less than 100 mm. The apparatus enables high deposition rate sputtering onto site-isolated regions on the substrate.

Abstract translation: 公开了用于将沉积层沉积到基底上的高沉积速率溅射的装置和方法。 设备通常包括处理室; 设置在处理室内的一个或多个溅射源，其中每个溅射源包括溅射靶; 设置在所述处理室内的衬底支撑件; 位于所述溅射源和所述衬底之间的屏蔽罩，所述屏蔽件包括位于每个溅射源下方的孔; 以及连接到所述基板支撑件的输送系统，其能够定位所述基板，使得所述基板上的多个位置隔离区域中的一个可以通过位于每个所述溅射源下方的所述孔暴露于溅射材料; 其中溅射靶和衬底之间的间距小于100mm。 该装置能够在衬底上的位置分离区域上实现高沉积速率溅射。

公开(公告)号：US08728879B2

公开(公告)日：2014-05-20

申请号：US13547856

申请日：2012-07-12

Applicant: Bob Kong ,  Tony Chiang ,  Chi-I Lang ,  Zhi-Wen Wen Sun ,  Jinhong Tong

Inventor： Bob Kong ,  Tony Chiang ,  Chi-I Lang ,  Zhi-Wen Wen Sun ,  Jinhong Tong

IPC: H01L21/20

CPC classification number: H01L21/02068 ,  C23C18/1651 ,  C23C18/54 ,  H01L21/288 ,  H01L21/76852 ,  H01L21/76874

Abstract: Embodiments of the current invention describe methods of processing a semiconductor substrate that include applying a zincating solution to the semiconductor substrate to form a zinc passivation layer on the titanium-containing layer, the zincating solution comprising a zinc salt, FeCl3, and a pH adjuster.

公开(公告)号：US08580584B2

公开(公告)日：2013-11-12

申请号：US13624102

申请日：2012-09-21

Applicant: Yun Wang ,  Tony P. Chiang ,  Chi-I Lang

Inventor： Yun Wang ,  Tony P. Chiang ,  Chi-I Lang

IPC: H01L21/00

CPC classification number: H01L51/0031 ,  H01L51/56

Abstract: A system and method of increasing productivity of OLED material screening includes providing a substrate that includes an organic semiconductor, processing regions on the substrate by combinatorially varying parameters associated with the OLED device production on the substrate, performing a first characterization test on the processed regions on the substrate to generate first results, processing regions on the substrate in a combinatorial manner by varying parameters associated with the OLED device production on the substrate based on the first results of the first characterization test, performing a second characterization test on the processed regions on the substrate to generate second results, and determining whether the substrate meets a predetermined quality threshold based on the second results.

Abstract translation: 提高OLED材料筛选的生产率的系统和方法包括提供包括有机半导体的衬底，通过组合地改变与衬底上的OLED器件生产相关的参数来在衬底上处理区域，对处理的区域进行第一表征测试 所述衬底产生第一结果，基于所述第一表征测试的第一结果，通过改变与所述衬底上的OLED器件生产相关联的参数，以组合方式处理所述衬底上的区域，对所述衬底上的所述处理区域进行第二特性测试 衬底以产生第二结果，以及基于第二结果确定衬底是否满足预定质量阈值。