公开(公告)号：US07956452B2

公开(公告)日：2011-06-07

申请号：US12461639

申请日：2009-08-19

申请人： Yun-Seok Choi ,  Hee-Seok Lee ,  Kyoung-Sei Choi

发明人： Yun-Seok Choi ,  Hee-Seok Lee ,  Kyoung-Sei Choi

IPC分类号： H01L23/48

CPC分类号： H01L21/563 ,  H01L23/295 ,  H01L23/60 ,  H01L24/16 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： Flip chip packages and methods of manufacturing the same are provided, the flip chip packages may include a package substrate, a semiconductor chip, conductive bumps, a ground pattern and an underfilling layer. The semiconductor chip may be over the package substrate. The conductive bumps may be between the semiconductor chip and the package substrate to electrically connect the semiconductor chip and the package substrate with each other. The ground pattern may ground one of the package substrate and the semiconductor chip. The underfilling layer may be between the package substrate and the semiconductor chip to surround the conductive bumps. The underfilling layer may have a diode selectively located between the ground pattern and the conductive bumps by electrostatic electricity applied to the underfilling layer to protect the semiconductor chip from the electrostatic electricity.

摘要翻译： 提供了倒装芯片封装及其制造方法，倒装芯片封装可以包括封装衬底，半导体芯片，导电凸块，接地图案和底部填充层。 半导体芯片可以在封装衬底之上。 导电凸块可以在半导体芯片和封装基板之间，以将半导体芯片和封装基板彼此电连接。 接地图可以将封装衬底和半导体芯片之一接地。 底部填充层可以在封装衬底和半导体芯片之间以包围导电凸块。 底部填充层可以通过施加到底部填充层的静电来选择性地位于接地图案和导电凸块之间的二极管，以保护半导体芯片免受静电。

公开(公告)号：US07868462B2

公开(公告)日：2011-01-11

申请号：US11541779

申请日：2006-10-03

申请人： Yun-Seok Choi ,  Hee-Seok Lee

发明人： Yun-Seok Choi ,  Hee-Seok Lee

IPC分类号： H01L23/538

CPC分类号： H01L25/0657 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/5227 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/05001 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01Q9/27 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A semiconductor package comprises a package board and a plurality of semiconductor chips sequentially stacked on the package board. Each of the semiconductor chips comprises a semiconductor substrate and an open loop-shaped chip line formed on the semiconductor substrate. The open loop-shaped chip line has first and second end portions. The first and second end portions of the open loop-shaped chip lines are electrically connected to each other by connectors, and the connectors and the open loop-shaped chip lines constitute a spiral antenna.

摘要翻译： 半导体封装包括封装板和顺序堆叠在封装板上的多个半导体芯片。 每个半导体芯片包括半导体衬底和形成在半导体衬底上的开环形芯片线。 开环状的芯片线具有第一和第二端部。 开环状芯片线的第一和第二端部通过连接器彼此电连接，并且连接器和开环形芯片线构成螺旋形天线。

公开(公告)号：US20080099887A1

公开(公告)日：2008-05-01

申请号：US11564760

申请日：2006-11-29

申请人： Eun-Seok SONG ,  Hee-Seok LEE

发明人： Eun-Seok SONG ,  Hee-Seok LEE

IPC分类号： H01L39/00

CPC分类号： H01L23/66 ,  H01L23/552 ,  H01L2223/6688 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/01322 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： Provided are a multi-ground shielding semiconductor package including analog and digital circuit blocks and capable of preventing a coupling problem between the analog and digital circuit blocks caused by high frequency noise. A method of fabricating the multi-ground shielding semiconductor package, and a method of preventing noise in the multi-ground shielding semiconductor package are also provided. The multi-ground shielding semiconductor package includes at least one semiconductor chip; and a circuit board on which the semiconductor chip is mounted and on which a plurality of circuit blocks are formed, wherein a conductive ground shielding is formed between the circuit blocks and separately from grounds of the circuit blocks to prevent noise between the circuit blocks.

摘要翻译： 提供了包括模拟和数字电路块并能够防止由高频噪声引起的模拟和数字电路块之间的耦合问题的多地屏蔽半导体封装。 还提供了一种制造多接地屏蔽半导体封装的方法，以及一种防止多接地屏蔽半导体封装中的噪声的方法。 多接地屏蔽半导体封装包括至少一个半导体芯片; 以及其上安装有半导体芯片的电路板，其上形成有多个电路块，其中在电路块之间形成导电接地屏蔽，并且与电路块的接地分离，以防止电路块之间的噪声。

公开(公告)号：US20080054261A1

公开(公告)日：2008-03-06

申请号：US11758176

申请日：2007-06-05

申请人： Eun-seok SONG ,  Dong-han KIM ,  Hee-seok LEE

发明人： Eun-seok SONG ,  Dong-han KIM ,  Hee-seok LEE

IPC分类号： H01L23/58 ,  G01R31/26

CPC分类号： G01R31/2884 ,  H01L22/32 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

摘要： A semiconductor package and testing method is disclosed. The package includes a substrate having top and bottom surfaces, a semiconductor chip mounted in a centrally located semiconductor chip mounting area of the substrate, and a plurality of test pads disposed on top and bottom surfaces of the substrate and comprising a first group of test pads configured on the top and bottom surfaces of the substrate and having a first height above the respective top and bottom surface of the substrate, and a second group of test pads disposed on the lower surface of the substrate and having a second height greater than the first, wherein each one of the second group of test pads includes a solder ball attached thereto.

摘要翻译： 公开了半导体封装和测试方法。 封装包括具有顶表面和底表面的衬底，安装在衬底的位于中心的半导体芯片安装区域中的半导体芯片以及设置在衬底的顶表面和底表面上的多个测试焊盘，并且包括第一组测试焊盘 配置在衬底的顶表面和底表面上并且具有在衬底的相应顶部和底部表面上方的第一高度，以及设置在衬底的下表面上并具有大于第一衬底的第二高度的第二组测试焊盘 其中第二组测试垫中的每一个包括附接到其上的焊球。

公开(公告)号：US07330084B2

公开(公告)日：2008-02-12

申请号：US11296769

申请日：2005-12-06

申请人： Hee-Seok Lee ,  Kyung-Lae Jang ,  Tae-Je Cho ,  Ki-Won Choi

发明人： Hee-Seok Lee ,  Kyung-Lae Jang ,  Tae-Je Cho ,  Ki-Won Choi

IPC分类号： H01P3/08

CPC分类号： H01P3/003 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48095 ,  H01L2224/4917 ,  H01L2224/49175 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/19107 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/3025 ,  H01P3/08 ,  H05K1/0219 ,  H05K3/222 ,  H05K2201/09236 ,  H05K2203/049 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/00 ,  H01L2924/013 ,  H01L2924/00013

摘要： A printed circuit board for a high-speed semiconductor package uses bonding wires as a shield structure, e.g., to shield an open portion of signal transmission lines, and thereby reduce the likelihood of coupling noises, e.g., between signal transmission lines.

摘要翻译： 用于高速半导体封装的印刷电路板使用接合线作为屏蔽结构，例如屏蔽信号传输线的开放部分，从而降低例如信号传输线之间耦合噪声的可能性。

公开(公告)号：US07327020B2

公开(公告)日：2008-02-05

申请号：US11033997

申请日：2005-01-13

申请人： Heung-Kyu Kwon ,  Hee-Seok Lee

发明人： Heung-Kyu Kwon ,  Hee-Seok Lee

IPC分类号： H01L23/02

CPC分类号： H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/16 ,  H01L29/0657 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4911 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2225/06582 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01072 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/10158 ,  H01L2924/10161 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/16153 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A multi-chip package, a semiconductor device used therein, and manufacturing method thereof are provided. The multi-chip package may include a substrate having a plurality of substrate bonding pads formed on an upper surface thereof, at least one first semiconductor chip mounted on the substrate, and at least one second semiconductor chip mounted on the substrate where the at least one first semiconductor chip may be mounted. The at least one second semiconductor chip may include at least one three-dimensional space so as to allow the at least one first semiconductor chip to be enclosed within the at least one three-dimensional space. The at least one three-dimensional space may be a cavity, a groove, or a combination thereof.

摘要翻译： 提供一种多芯片封装，其中使用的半导体器件及其制造方法。 多芯片封装可以包括具有形成在其上表面上的多个衬底焊盘的衬底，安装在衬底上的至少一个第一半导体芯片以及安装在衬底上的至少一个第二半导体芯片，其中至少一个 可以安装第一半导体芯片。 至少一个第二半导体芯片可以包括至少一个三维空间，以便允许至少一个第一半导体芯片封装在至少一个三维空间内。 所述至少一个三维空间可以是空腔，凹槽或其组合。

公开(公告)号：US20080023844A1

公开(公告)日：2008-01-31

申请号：US11819628

申请日：2007-06-28

申请人： Yun-seok Choi ,  Na-rae Shin ,  Hee-seok Lee

发明人： Yun-seok Choi ,  Na-rae Shin ,  Hee-seok Lee

IPC分类号： H01L23/52

CPC分类号： H05K1/165 ,  H01L2924/0002 ,  H05K1/0216 ,  H05K1/0233 ,  H05K1/0237 ,  H05K2201/09236 ,  H05K2201/09263 ,  H01L2924/00

摘要： Example embodiments relate to an interconnection substrate and a semiconductor chip package and a display system including the same. The interconnection substrate may include a base film, a signal line provided on the base film, a power line provided on the base film as a line pattern including a plurality of bent portions, and a ground line provided on the base film in parallel with the power line. The interconnection substrate may further include a semiconductor chip provided on the base film, wherein the power, ground, and/or signal lines are electrically connected to the semiconductor chip to form a semiconductor chip package. A display system may include the above semiconductor chip package, a screen displaying an image, and a PCB generating a signal. The semiconductor chip may be connected between the PCB and the screen and relay the generated signal from the PCB to the screen. Use of the power, ground, and/or signal lines having a plurality of bent portions may reduce electromagnetic interference (EMI) within the display system.

摘要翻译： 示例性实施例涉及互连衬底和半导体芯片封装以及包括其的显示系统。 互连基板可以包括基膜，设置在基膜上的信号线，设置在基膜上的电源线作为包括多个弯曲部的线图案，以及设置在基膜上的与线平行的接地线 电源线。 互连基板还可以包括设置在基膜上的半导体芯片，其中电源，接地和/或信号线电连接到半导体芯片以形成半导体芯片封装。 显示系统可以包括上述半导体芯片封装，显示图像的屏幕和产生信号的PCB。 半导体芯片可以连接在PCB和屏幕之间，并将产生的信号从PCB继电器传递到屏幕。 使用具有多个弯曲部分的电源，接地和/或信号线可以减少显示系统内的电磁干扰（EMI）。

公开(公告)号：US20080018390A1

公开(公告)日：2008-01-24

申请号：US11779324

申请日：2007-07-18

申请人： Hee-seok LEE ,  Yun-seok CHOI ,  Eun-seok SONG ,  Young-sang CHO ,  Na-rae SHIN

发明人： Hee-seok LEE ,  Yun-seok CHOI ,  Eun-seok SONG ,  Young-sang CHO ,  Na-rae SHIN

IPC分类号： H01F21/12 ,  H01F27/25

CPC分类号： H01F21/12 ,  H01F41/045 ,  H05K1/147 ,  H05K1/165

摘要： An adjustable-inductance (AI) filter, a tape distribution substrate including the filter, and a display panel assembly including the tape distribution substrate are provided. The adjustable-inductance (AI) filter includes a filter distribution line including first and second end portions each having a first line width, at least one repair pattern having a second line width and disposed between the first and second end portions, and at least one unit filter bank connected in parallel to the at least one repair pattern, respectively.

摘要翻译： 提供可调电感（AI）滤波器，包括滤波器的带分配基板以及包括带分布基板的显示面板组件。 可调电感（AI）滤波器包括滤波器分配线，滤波器分配线包括每个具有第一线宽度的第一和第二端部，具有第二线宽并且设置在第一和第二端部之间的至少一个修复图案，以及至少一个 单元滤波器组分别与所述至少一个修复模式并联连接。

公开(公告)号：US20070285188A1

公开(公告)日：2007-12-13

申请号：US11761416

申请日：2007-06-12

申请人： Eun-seok SONG ,  Hee-seok LEE ,  So-young LIM

发明人： Eun-seok SONG ,  Hee-seok LEE ,  So-young LIM

IPC分类号： H04B3/28

CPC分类号： H01Q15/006

摘要： A substrate for a semiconductor package comprises a dielectric substrate, a circuit pattern, and an electromagnetic band gap (EBG) pattern. The circuit pattern is formed on a first surface of the dielectric substrate and is connected to ground via a ground connection. The electromagnetic band gap (EBG) pattern comprises a plurality of zigzag unit structures formed on a second surface of the dielectric substrate, wherein the second surface is formed on an opposite side of the dielectric substrate from the first surface; the zigzag unit structures are electrically connected to each other; and at least one of the zigzag unit structures is electrically connected to the ground connection.

摘要翻译： 用于半导体封装的衬底包括电介质衬底，电路图案和电磁带隙（EBG）图案。 电路图案形成在电介质基板的第一表面上，并通过接地连接接地。 电磁带隙（EBG）图案包括形成在电介质基板的第二表面上的多个之字形单元结构，其中第二表面形成在电介质基板的与第一表面相反的一侧上; 之字形单元结构彼此电连接; 并且所述之字形单元结构中的至少一个电连接到所述接地连接。

公开(公告)号：US20060097365A1

公开(公告)日：2006-05-11

申请号：US11258672

申请日：2005-10-25

申请人： Eun-Seok Song ,  Hee-Seok Lee

发明人： Eun-Seok Song ,  Hee-Seok Lee

IPC分类号： H01L23/495

CPC分类号： H01L24/49 ,  H01L23/3128 ,  H01L23/50 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/16 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/85051 ,  H01L2224/85986 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/85186 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2224/4554

摘要： A semiconductor package features a ring-shaped silicon decoupling capacitor that reduces simultaneous switching noise. The decoupling capacitor is fabricated on a substrate from silicon using a wafer fabrication process and takes the form of an annular capacitive structure that extends around a periphery of a substrate-mounted integrated circuit (IC). The decoupling capacitor has a reduced thickness on or below a chip level and takes the place of a conventional power/ground ring. Therefore, the decoupling capacitor can be disposed within the package without increasing the thickness and the size of the package. The decoupling capacitor may be coupled to various power pins, allowing optimum wire bonding, shortened electrical connections, and reduced inductance. Bonding wires connected to the decoupling capacitor have higher specific resistance, lowering the peak of the resonance frequency and thereby reducing simultaneous switching noise.