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    Non-volatile memory with reduced word line switch area
    45.
    发明授权
    Non-volatile memory with reduced word line switch area 有权

    公开(公告)号：US12032837B2

    公开(公告)日：2024-07-09

    申请号：US17957424

    申请日：2022-09-30

    Applicant: SanDisk Technologies LLC

    Inventor： Yuki Mizutani ,  Kazutaka Yoshizawa ,  Kiyokazu Shishido ,  Eiichi Fujikura

    IPC: G06F3/06

    CPC classification number: G06F3/0626 ,  G06F3/0629 ,  G06F3/0679

    Abstract: A three dimensional non-volatile memory structure includes word lines connected to non-volatile memory cells arranged in blocks. A plurality of word line switches are connected to the word lines and one or more sources of voltage. The word line switches are arranged in groups of X word line switches such that each group of X word line switches is positioned in a line under Y blocks of non-volatile memory cells and has a length that is equal to the width of the Y blocks of non-volatile memory cells. To allow closer placement of word line switches that supply different blocks and support the possible large voltage differences between their transistors, word line switches supplying different blocks are formed over a single active region and separated by an intermediate control gate set to be off.

    Methods and systems for selectively enabling/disabling memory dies
    49.
    发明授权
    Methods and systems for selectively enabling/disabling memory dies 有权

    公开(公告)号：US12020774B2

    公开(公告)日：2024-06-25

    申请号：US17832479

    申请日：2022-06-03

    Applicant: SanDisk Technologies LLC

    Inventor： Sneha Bhatia ,  Sajal Mittal ,  Venkatesh Prasad Ramachandra ,  Anil Pai

    IPC: G11C7/22 ,  G11C7/10

    CPC classification number: G11C7/222 ,  G11C7/1039 ,  G11C7/1063 ,  G11C7/109

    Abstract: Systems and methods disclosed herein provide for selectively activating or deactivating one or more memory of a memory array, such that related data path logic of deactivated memory dies neither detects nor processes control signals or data signals for data operations. Examples of the systems and methods provided herein operate to detect a first enable signal at a memory die and detect a first data signal on input/output (I/O) receivers of the memory die. Responsive to detecting at least the first enable signal, a bit value encoded in the first data signal is latched to obtain a first bit pattern. A second bit pattern is obtained, and, based on a comparison of the first bit pattern to the second bit pattern, the I/O receivers of the memory die are activated.

    THREE-DIMENSIONAL NOR ARRAY AND METHOD OF MAKING THE SAME
    50.
    发明公开
    THREE-DIMENSIONAL NOR ARRAY AND METHOD OF MAKING THE SAME 审中-公开

    公开(公告)号：US20240206171A1

    公开(公告)日：2024-06-20

    申请号：US18352025

    申请日：2023-07-13

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Masaaki HIGASHITANI ,  Peter RABKIN ,  Hiroyuki KINOSHITA ,  Satoshi SHIMIZU ,  Yanli ZHANG ,  Johann ALSMEIER

    IPC: H10B43/27 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H10B43/30

    CPC classification number: H10B43/27 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H10B43/30

    Abstract: A semiconductor structure includes a vertical stack of repetition units, where each instance of the repetition unit extends along a first horizontal direction and includes a first electrically conductive strip, a first memory film located over the first electrically conductive strip, discrete semiconductor channels that are laterally spaced apart from each other along the first horizontal direction and located above the first memory film, a second memory film located above the discrete semiconductor channels, a second electrically conductive strip located above the second memory film, and an insulating strip located above the first electrically conductive strip. Source/drain openings are arranged along the first horizontal direction, interlaced with the discrete semiconductor channels, and vertically extending through the vertical stack of repetition units, and source/drain pillar structures are located in respective source/drain openings, and vertically extending through the vertical stack of repetition units.

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