公开(公告)号：US10256322B2

公开(公告)日：2019-04-09

申请号：US15926921

申请日：2018-03-20

Applicant: Applied Materials, Inc.

Inventor： Xinyu Bao ,  Zhiyuan Ye ,  Hua Chung

IPC: H01L21/00 ,  H01L29/66 ,  H01L29/78 ,  H01L29/167 ,  H01L29/08 ,  H01L29/06

Abstract: A device comprising Si:As source and drain extensions and Si:As or Si:P source and drain features formed using selective epitaxial growth and a method of forming the same is provided. The epitaxial layers used for the source and drain extensions and the source and drain features herein are deposited by simultaneous film formation and film etching, wherein the deposited material on the monocrystalline layer is etched at a slower rate than deposition material deposited on non-monocrystalline location of a substrate. As a result, an epitaxial layer is deposited on the monocrystalline surfaces, and a layer is not deposited on non-monocrystalline surfaces of the same base material, such as silicon.

公开(公告)号：US10205002B2

公开(公告)日：2019-02-12

申请号：US15418128

申请日：2017-01-27

Applicant: Applied Materials, Inc.

Inventor： Xinyu Bao ,  Chun Yan ,  Errol Antonio C. Sanchez ,  Hua Chung

IPC: C23C16/455 ,  C30B25/02 ,  C30B25/04 ,  C30B25/16 ,  C30B25/18 ,  H01L21/02 ,  H01L21/24 ,  H01L21/762 ,  H01L29/04 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

Abstract: The present disclosure generally relate to methods of processing a substrate in an epitaxy chamber. The method includes exposing a substrate having one or more fins to a group IV-containing precursor and a surfactant containing antimony to form an epitaxial film over sidewalls of the one or more fin structures, wherein the surfactant containing antimony is introduced into the epitaxy chamber before epitaxial growth of the epitaxial film, and a molar ratio of the surfactant containing antimony to the group IV-containing precursor is about 0.0001 to about 10.

公开(公告)号：US10128110B2

公开(公告)日：2018-11-13

申请号：US15882939

申请日：2018-01-29

Applicant: Applied Materials, Inc.

Inventor： Abhishek Dube ,  Xuebin Li ,  Yi-Chiau Huang ,  Hua Chung ,  Schubert S. Chu

IPC: H01L21/02

Abstract: Embodiments of the present disclosure generally relate to methods for forming a doped silicon epitaxial layer on semiconductor devices at increased pressure and reduced temperature. In one embodiment, the method includes heating a substrate disposed within a processing chamber to a temperature of about 550 degrees Celsius to about 800 degrees Celsius, introducing into the processing chamber a silicon source comprising trichlorosilane (TCS), a phosphorus source, and a gas comprising a halogen, and depositing a silicon containing epitaxial layer comprising phosphorus on the substrate, the silicon containing epitaxial layer having a phosphorus concentration of about 1×1021 atoms per cubic centimeter or greater, wherein the silicon containing epitaxial layer is deposited at a chamber pressure of about 150 Torr or greater.

公开(公告)号：US09966438B2

公开(公告)日：2018-05-08

申请号：US15418286

申请日：2017-01-27

Applicant: Applied Materials, Inc.

Inventor： Yi-Chiau Huang ,  Hua Chung ,  Sheng-Chin Kung ,  Xuebin Li

IPC: H01L21/02 ,  H01L29/167 ,  H01L29/161 ,  H01L21/225 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/20 ,  H01L21/203 ,  H01L21/205

CPC classification number: H01L29/167 ,  H01L21/02057 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/02656 ,  H01L21/02661 ,  H01L21/02667 ,  H01L21/2018 ,  H01L21/2033 ,  H01L21/2053 ,  H01L21/2252 ,  H01L21/26513 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/67184 ,  H01L21/67207 ,  H01L29/161 ,  H01L29/785

Abstract: Implementations described herein generally relate to methods and systems for depositing layer on substrates, and more specifically, to methods for forming boron or gallium-doped germanium on silicon-containing surfaces. In one implementation, a method of processing a substrate is provided. The method comprises exposing a substrate having an exposed silicon-germanium surface and an exposed dielectric surface to a pre-treatment process, selectively depositing a boron-doped or a gallium-doped layer on the exposed silicon-germanium surface and exposing the substrate to a post-treatment process.

公开(公告)号：US09929055B2

公开(公告)日：2018-03-27

申请号：US15391623

申请日：2016-12-27

Applicant: Applied Materials, Inc.

Inventor： Abhishek Dube ,  Hua Chung ,  Jenn-Yue Wang ,  Xuebin Li ,  Yi-Chiau Huang ,  Schubert S. Chu

IPC: H01L21/20 ,  H01L21/8234 ,  H01L21/02 ,  H01L29/78 ,  H01L21/3065

CPC classification number: H01L21/823431 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02513 ,  H01L21/02516 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/3065 ,  H01L29/7848 ,  H01L29/7851

Abstract: Implementations of the present disclosure generally relate to methods for epitaxial growth of a silicon material on an epitaxial film. In one implementation, the method includes forming an epitaxial film over a semiconductor fin, wherein the epitaxial film includes a top surface having a first facet and a second facet, and forming an epitaxial layer on at least the top surface of the epitaxial film by alternatingly exposing the top surface to a first precursor gas comprising one or more silanes and a second precursor gas comprising one or more chlorinated silanes at a temperature of about 375° C. to about 450° C. and a chamber pressure of about 5 Torr to about 20 Torr.

公开(公告)号：US09508831B2

公开(公告)日：2016-11-29

申请号：US14320597

申请日：2014-06-30

Applicant: Applied Materials, Inc.

Inventor： Ying Zhang ,  Hua Chung

IPC: H01L21/00 ,  H01L29/66 ,  H01L21/311 ,  H01L29/06 ,  H01L29/10 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/16 ,  H01L29/161 ,  H01L21/265 ,  H01L21/324 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/775

CPC classification number: H01L29/66795 ,  B82Y10/00 ,  B82Y40/00 ,  H01J37/32357 ,  H01J37/32449 ,  H01J37/32541 ,  H01J37/32568 ,  H01L21/02233 ,  H01L21/02236 ,  H01L21/02252 ,  H01L21/02359 ,  H01L21/02603 ,  H01L21/02606 ,  H01L21/265 ,  H01L21/30621 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/31116 ,  H01L21/324 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/66666 ,  H01L29/775

Abstract: Embodiments of the present disclosure provide methods for forming nanowire structures with desired materials for three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips. In one example, a method of forming nanowire structures on a substrate includes in a suspended nanowire structure on a substrate, the suspended nanowire includes multiple material layers having a spaced apart relationship repeatedly formed in the suspended nanowire structure, wherein the material layer includes a coating layer coated on an outer surface of a main body formed in the material layer, selectively removing a first portion of the coating layer from the material layers to expose the underlying main body of the material layers while maintaining a second portion of the coating layer remaining on the material layers, laterally etching the main body of the material layers exposed by removal of the coating layer, and selectively growing film layers on the exposed main body of the material layer.

Abstract translation: 本公开的实施例提供了用于形成用于半导体芯片的鳍式场效应晶体管（FinFET）的三维（3D）堆叠的所需材料的纳米线结构的方法。 在一个实例中，在衬底上形成纳米线结构的方法包括在衬底上的悬浮的纳米线结构中，悬浮的纳米线包括在悬浮的纳米线结构中重复形成间隔关系的多个材料层，其中材料层包括涂层 层涂覆在形成在材料层中的主体的外表面上，从材料层选择性地去除涂层的第一部分，以暴露材料层的下面的主体，同时保持涂层的第二部分保持在 材料层，横向蚀刻通过去除涂层而暴露的材料层的主体，以及选择性地在材料层的暴露的主体上生长膜层。

公开(公告)号：US09401310B2

公开(公告)日：2016-07-26

申请号：US14170887

申请日：2014-02-03

Applicant: Applied Materials, Inc.

Inventor： Ying Zhang ,  Hua Chung

IPC: H01L21/8234 ,  H01L21/033 ,  H01L21/311

CPC classification number: H01L21/823431 ,  H01L21/0334 ,  H01L21/0337 ,  H01L21/31144 ,  H01L29/66795

Abstract: Embodiments may include a method of semiconductor patterning including forming a first trench bordered by a first spacer material. The method may involve forming a second trench bordered by a second spacer material formed conformally around the first spacer material. The method may include filling the second trench with a semiconductor material.

Abstract translation: 实施例可以包括半导体图案化的方法，包括形成由第一间隔物材料边界的第一沟槽。 该方法可以包括形成由第一间隔物材料保形地形成的第二间隔物材料边界的第二沟槽。 该方法可以包括用半导体材料填充第二沟槽。

公开(公告)号：US20150221556A1

公开(公告)日：2015-08-06

申请号：US14170887

申请日：2014-02-03

Applicant: Applied Materials, Inc.

Inventor： Ying Zhang ,  Hua Chung

IPC: H01L21/8234 ,  H01L21/033 ,  H01L21/02

CPC classification number: H01L21/823431 ,  H01L21/0334 ,  H01L21/0337 ,  H01L21/31144 ,  H01L29/66795

Abstract: Embodiments may include a method of semiconductor patterning including forming a first trench bordered by a first spacer material. The method may involve forming a second trench bordered by a second spacer material formed conformally around the first spacer material. The method may include filling the second trench with a semiconductor material.

Abstract translation: 实施例可以包括半导体图案化的方法，包括形成由第一间隔物材料边界的第一沟槽。 该方法可以包括形成由第一间隔物材料保形地形成的第二间隔物材料边界的第二沟槽。 该方法可以包括用半导体材料填充第二沟槽。