公开(公告)号：US06555459B1

公开(公告)日：2003-04-29

申请号：US09491033

申请日：2000-01-25

申请人： Ryoji Tokushige ,  Nobuyuki Takai ,  Hiroyuki Shinogi ,  Seiichi Ono

发明人： Ryoji Tokushige ,  Nobuyuki Takai ,  Hiroyuki Shinogi ,  Seiichi Ono

IPC分类号： H01L2100

CPC分类号： H01L24/12 ,  H01L23/3114 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/051 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/13006 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2224/05552 ,  H01L2924/00014 ,  H01L2924/013 ,  H01L2924/01083

摘要： A metal post used with a chip size package and barrier metal formed on the metal post are omitted. After a second opening where a wiring layer is exposed is made, a second seed layer is formed and a solder post 7 is formed with the seed layer as a plate electrode.

摘要翻译： 省略了在金属柱上形成的具有芯片尺寸封装和阻挡金属的金属柱。 在布线层暴露的第二开口之后，形成第二种子层，并且形成具有种子层作为平板电极的焊料柱7。

公开(公告)号：US08373278B2

公开(公告)日：2013-02-12

申请号：US12048861

申请日：2008-03-14

申请人： Hiroyuki Shinogi

发明人： Hiroyuki Shinogi

IPC分类号： H01L23/48

CPC分类号： H01L25/0657 ,  H01L22/10 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/481 ,  H01L24/16 ,  H01L24/90 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/90 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： Semiconductor dice judged as good dice are stacked on a base substrate in which through holes and through hole electrodes are formed. Next, a protection layer to cover the semiconductor dice is formed. It is preferable that the protection layer is composed of a plurality of resin layers (a first resin layer and a second resin layer) that are different, in hardness from each other. Then, a conductive terminal that is connected with the through hole electrode is formed on a back surface of the base substrate. Next, the second resin layer and the base substrate are cut along predetermined dicing lines and separated into individual semiconductor devices in chip form. A process step of separation into the semiconductor devices is performed while each of the semiconductor dice is mounted on the base substrate in wafer form.

摘要翻译： 判断为好的骰子的半导体骰子堆叠在形成有通孔和通孔电极的基底基板上。 接下来，形成覆盖半导体晶片的保护层。 保护层优选由彼此硬度不同的多个树脂层（第一树脂层和第二树脂层）构成。 然后，在基底基板的背面形成有与通孔电极连接的导电端子。 接下来，沿着预定的切割线切割第二树脂层和基底基板，并以芯片形式分离成单独的半导体器件。 在半导体芯片中的每一个以晶片形式安装在基底基板上的同时执行分离到半导体器件中的处理步骤。

公开(公告)号：US20090321903A1

公开(公告)日：2009-12-31

申请号：US12438888

申请日：2007-08-22

申请人： Hiroyuki Shinogi ,  Katsuhiko Kitagawa ,  Kazuo Okada ,  Hiroshi Yamada

发明人： Hiroyuki Shinogi ,  Katsuhiko Kitagawa ,  Kazuo Okada ,  Hiroshi Yamada

IPC分类号： H01L23/02 ,  H01L21/50

CPC分类号： H01L27/14618 ,  B81C1/00269 ,  H01L23/315 ,  H01L27/14625 ,  H01L27/14685 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/00

摘要： This invention is directed to offer a semiconductor device in which a cavity space is easily provided in a specific region when a supporting member is bonded to a semiconductor substrate through an adhesive layer, and its manufacturing method. A resist layer is applied to an entire top surface of the semiconductor substrate 2, and exposure to transfer a pattern is performed. By subsequent development and selective removal of the resist layer, the resist layer is formed into a shape of a plurality of columnar structures 4. Then, an adhesive material made of an epoxy resin or the like is applied to the entire top surface of the semiconductor substrate 2. The adhesive material is gathered around the columnar structures 4 by itself to form an adhesive layer 5. Therefore, in contrast, the adhesive layer 5 does not deposit in a region where the cavity is to be formed. Then, the supporting member 6 is bonded through the columnar structures 4 and the adhesive layer 5. By bonding the supporting member 6, there is formed the cavity 7 surrounded with the semiconductor substrate 2, the columnar structures 3 and the supporting member 6.

摘要翻译： 本发明旨在提供一种半导体器件及其制造方法，其中当支撑构件通过粘合剂层结合到半导体衬底时，在特定区域中容易设置空腔。 将抗蚀剂层施加到半导体衬底2的整个顶表面，并且进行曝光以转印图案。 通过随后的抗蚀剂层的显影和选择性去除，将抗蚀剂层形成为多个柱状结构体4的形状。然后，将由环氧树脂等制成的粘合剂材料施加到半导体的整个顶表面 基材2.粘合剂材料自身聚集在柱状结构4周围以形成粘合剂层5.因此，相反，粘合剂层5不会沉积在要形成空腔的区域中。 然后，支撑部件6通过柱状结构体4和粘合剂层5接合。通过粘合支撑部件6，形成有被半导体基板2，柱状结构体3和支撑部件6包围的空腔7。

公开(公告)号：US20080265441A1

公开(公告)日：2008-10-30

申请号：US12104516

申请日：2008-04-17

申请人： Kazuo Okada ,  Hiroyuki Shinogi ,  Yoshinori Seki ,  Hiroshi Yamada

发明人： Kazuo Okada ,  Hiroyuki Shinogi ,  Yoshinori Seki ,  Hiroshi Yamada

IPC分类号： H01L23/48 ,  H01L21/00

CPC分类号： H01L24/97 ,  H01L24/05 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L27/14618 ,  H01L27/14683 ,  H01L29/0657 ,  H01L2224/0401 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12043 ,  H01L2924/15311 ,  H01L2924/00

摘要： The invention enhances moisture resistance between a supporting body and an adhesive layer to enhance the reliability of a semiconductor device. A semiconductor device of the invention has a first insulation film formed on a semiconductor element, a first wiring formed on the first insulation film, a supporting body formed on the semiconductor element with an adhesive layer being interposed therebetween, a third insulation film covering the back surface of the semiconductor element onto the side surface thereof and the side surface of the adhesive layer, a second wiring connected to the first wiring and extending onto the back surface of the semiconductor element with the third insulation film being interposed therebetween, and a protection film formed on the second wiring.

摘要翻译： 本发明提高了支撑体和粘合剂层之间的耐湿性，以提高半导体器件的可靠性。 本发明的半导体器件具有形成在半导体元件上的第一绝缘膜，形成在第一绝缘膜上的第一布线，形成在半导体元件上的支撑体，其间夹有粘合剂层，覆盖背面的第三绝缘膜 半导体元件的侧表面和粘合剂层的侧表面上的第二布线，连接到第一布线并且延伸到半导体元件的背表面上并且第三绝缘膜插入其间的第二布线，以及保护膜 形成在第二布线上。

公开(公告)号：US06424051B1

公开(公告)日：2002-07-23

申请号：US09500271

申请日：2000-02-08

申请人： Hiroyuki Shinogi ,  Nobuyuki Takai ,  Ryoji Tokushige ,  Katsuhiko Kitagawa

发明人： Hiroyuki Shinogi ,  Nobuyuki Takai ,  Ryoji Tokushige ,  Katsuhiko Kitagawa

IPC分类号： H01L2328

CPC分类号： H01L23/564 ,  H01L23/3185 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： To improve the moisture resistance of a chip size package, a seal ring 4 is made up of tungsten plugs and metal electrodes 11 and 12. Further, a spacer is formed on both or either of a first flank 13 and a second flank 14. The spacer can be formed on all interlayer insulating films extended to a dicing line part 3, whereby multiple seal rings can be provided.

摘要翻译： 为了提高芯片尺寸封装的耐湿性，密封环4由钨插头和金属电极11和12组成。此外，在第一侧面13和第二侧面14两者上形成间隔件。 可以在延伸到切割线部分3的所有层间绝缘膜上形成间隔物，从而可以提供多个密封环。

公开(公告)号：US06717243B2

公开(公告)日：2004-04-06

申请号：US10183980

申请日：2002-06-28

申请人： Hiroyuki Shinogi ,  Toshimitsu Taniguchi

发明人： Hiroyuki Shinogi ,  Toshimitsu Taniguchi

IPC分类号： H01L23495

CPC分类号： H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05093 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2924/0001 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01033 ,  H01L2924/01059 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/12041 ,  H01L2924/13091 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor device has a bump electrode formed on a flat surface of a passivation film of the device. The bump electrode is connected to a top wiring layer through a plurality of openings in the passivation film underneath the bump electrode, which are filled with a conductive material. The bump electrode is formed away from via holes, which connects the top wiring layer for the bump electrode and a lower wiring layer connected to source and drain layers of the device.

摘要翻译： 半导体器件具有在器件的钝化膜的平坦表面上形成的凸块电极。 突起电极通过突起电极下面的钝化膜中的多个开口连接到顶部布线层，该多个开口填充有导电材料。 突起电极形成为远离通孔，其连接凸起电极的顶部布线层和连接到器件的源极和漏极层的下部布线层。

公开(公告)号：US06479900B1

公开(公告)日：2002-11-12

申请号：US09468414

申请日：1999-12-20

申请人： Hiroyuki Shinogi ,  Nobuyuki Takai ,  Ryoji Tokushige

发明人： Hiroyuki Shinogi ,  Nobuyuki Takai ,  Ryoji Tokushige

IPC分类号： H01L2348

CPC分类号： H01L23/53295 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/5329 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/11 ,  H01L2224/11334 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

摘要： A dielectric resin layer R covers a wiring layer 7 and a metal post 8 which are made of Cu. The dielectric resin layer is made of shrinkable resin whose film thickness is greatly reduced during thermal setting. This makes it unnecessary to perform a step of grinding the dielectric resin layer to expose a head of the metal post.

摘要翻译： 介电树脂层R覆盖由Cu制成的布线层7和金属柱8。 电介质树脂层由在热定型期间其膜厚度大大降低的可收缩树脂制成。 这使得不需要进行研磨电介质树脂层以暴露金属柱的头部的步骤。

公开(公告)号：US20090026610A1

公开(公告)日：2009-01-29

申请号：US12177696

申请日：2008-07-22

申请人： Katsuhiko Kitagawa ,  Hiroyuki Shinogi

发明人： Katsuhiko Kitagawa ,  Hiroyuki Shinogi

IPC分类号： H01L23/48 ,  H01L21/58

CPC分类号： H01L23/5389 ,  H01L21/6836 ,  H01L23/3121 ,  H01L23/3185 ,  H01L24/12 ,  H01L2221/68327 ,  H01L2224/16 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/12044 ,  H01L2924/14

摘要： The invention provides a semiconductor device having high reliability and a method of manufacturing the same. The semiconductor device of the invention has pad electrodes formed on a semiconductor die near the side surface portion thereof and connected to a semiconductor integrated circuit or the like in the semiconductor die, a supporting body formed on the pad electrodes, an insulation film formed on the side and back surface portions of the semiconductor die, wiring layers connected to the back surfaces of the pad electrodes and extending from the side surface portion onto the back surface portion of the semiconductor die so as to contact the insulation film, and a second protection film formed on the side surface portion of the supporting body.

摘要翻译： 本发明提供一种具有高可靠性的半导体器件及其制造方法。 本发明的半导体器件具有形成在半导体管芯的侧表面部分上的焊盘电极，并连接到半导体管芯中的半导体集成电路等，形成在焊盘电极上的支撑体，形成在半导体芯片上的绝缘膜 半导体管芯的侧表面部分和背表面部分，连接到焊盘电极的背表面并且从侧表面部分延伸到半导体管芯的背表面部分以与绝缘膜接触的布线层，以及第二保护膜 形成在支撑体的侧面部上。

公开(公告)号：US06656758B1

公开(公告)日：2003-12-02

申请号：US09684604

申请日：2000-10-06

申请人： Hiroyuki Shinogi ,  Ryoji Tokushige ,  Nobuyuki Takai

发明人： Hiroyuki Shinogi ,  Ryoji Tokushige ,  Nobuyuki Takai

IPC分类号： H01L2100

CPC分类号： H01L24/12 ,  H01L23/3114 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05644 ,  H01L2224/13099 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014

摘要： First, a passivation film 3 having an opening K from which a part of the Al electrode 1 formed through an interlayer insulating film 2 made of a BPSG film is exposed is formed on a wafer. A wiring layer 7, which is connected to the Al electrode 1 exposed from the opening K and extended to the upper surface of the wafer, is formed. After a metal post 8 is formed on the wiring layer 7, a first groove TC1, which is located on the periphery of the chip inclusive of the wiring layer 7 and half cuts the wafer, is formed. The upper portion of the interlayer insulating film 2 is isotropically etched through the first groove TC1 to form a second groove TC2 having a larger opening diameter than that of the first groove TC1. The wafer surface inclusive of the wiring layer 7, second groove TC2 and first groove TC1 is resin-sealed to form an insulating resin layer R. Thereafter, a solder ball 12 is formed on the metal post 8 exposed from the insulating resin layer R. Finally, the wafer is fully cut through the insulating resin layer R formed in the first and the second grooves TC1 and TC2.

摘要翻译： 首先，在晶片上形成具有通过由BPSG膜构成的层间绝缘膜2而形成的Al电极1的一部分露出的开口K的钝化膜3。 形成与从开口K露出并延伸到晶片的上表面的Al电极1连接的布线层7。 在布线层7上形成金属柱8之后，形成位于包括布线层7在内的芯片周边的第一沟槽TC1，并切割半晶片。 层间绝缘膜2的上部通过第一沟槽TC1进行各向同性蚀刻，以形成具有比第一沟槽TC1的开口直径大的开口直径的第二沟槽TC2。 包括布线层7，第二沟槽TC2和第一沟槽TC1的晶片表面被树脂密封以形成绝缘树脂层R.之后，在暴露于绝缘树脂层R的金属柱8上形成焊球12。 最后，通过形成在第一和第二槽TC1和TC2中的绝缘树脂层R，完全切割晶片。

公开(公告)号：US07944015B2

公开(公告)日：2011-05-17

申请号：US12177696

申请日：2008-07-22

申请人： Katsuhiko Kitagawa ,  Hiroyuki Shinogi

发明人： Katsuhiko Kitagawa ,  Hiroyuki Shinogi

IPC分类号： H01L31/113

CPC分类号： H01L23/5389 ,  H01L21/6836 ,  H01L23/3121 ,  H01L23/3185 ,  H01L24/12 ,  H01L2221/68327 ,  H01L2224/16 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/12044 ,  H01L2924/14

摘要： The invention provides a semiconductor device having high reliability and a method of manufacturing the same. The semiconductor device of the invention has pad electrodes formed on a semiconductor die near the side surface portion thereof and connected to a semiconductor integrated circuit or the like in the semiconductor die, a supporting body formed on the pad electrodes, an insulation film formed on the side and back surface portions of the semiconductor die, wiring layers connected to the back surfaces of the pad electrodes and extending from the side surface portion onto the back surface portion of the semiconductor die so as to contact the insulation film, and a second protection film formed on the side surface portion of the supporting body.

摘要翻译： 本发明提供一种具有高可靠性的半导体器件及其制造方法。 本发明的半导体器件具有形成在半导体管芯的侧表面部分上的焊盘电极，并连接到半导体管芯中的半导体集成电路等，形成在焊盘电极上的支撑体，形成在半导体芯片上的绝缘膜 半导体管芯的侧表面部分和背表面部分，连接到焊盘电极的背表面并且从侧表面部分延伸到半导体管芯的背表面部分以与绝缘膜接触的布线层，以及第二保护膜 形成在支撑体的侧面部上。