公开(公告)号：US06672759B2

公开(公告)日：2004-01-06

申请号：US09112593

申请日：1998-07-09

申请人： Claudius Feger

发明人： Claudius Feger

IPC分类号： G01N2516

CPC分类号： G01N25/16

摘要： The present invention is a method to eliminate the influence of clamp dimensional changes on the displacement measurement during the measurement of the coefficient of thermal expansion (CTE) of samples in tension. In a first embodiment clamp dimensional changes can be eliminated by making clamps from a material with near zero CTEs. In another embodiment clamp dimensional changes can be reduced by minimizing the CTE of the clamp material. Finally clamp dimensional changes are taken into account. This is achieved directly by subtracting a prerecorded baseline from the measurements; or by determining the CTE measurement for various sample lengths and obtaining the slope of a straight line through the points on a MD (measured displacement)/DT (temperature range of displacement measurement) versus sample length plot. The slope is the corrected CTE. Clamp dimensional changes can also be taken into account indirectly by obtaining a clamp displacement contribution (CDC) factor which allows to correct measured displacements to result the correct CTE.

摘要翻译： 本发明是一种在拉伸样品的热膨胀系数（CTE）测量期间消除夹具尺寸变化对位移测量的影响的方法。 在第一实施例中，可以通过从具有接近零CTE的材料制造夹具来消除尺寸变化。 在另一个实施例中，可以通过使夹紧材料的CTE最小化来减小尺寸变化。 最后夹紧尺寸变化被考虑在内。 这是通过从测量中减去预先记录的基线直接实现的; 或通过确定各种样品长度的CTE测量，并通过MD（测量位移）/ DT（位移测量的温度范围）与样品长度图获得直线的斜率。 斜率是校正后的CTE。 也可以通过获得钳位位移贡献（CDC）因子间接考虑钳位尺寸变化，这允许校正测量的位移以产生正确的CTE。

公开(公告)号：US4846929A

公开(公告)日：1989-07-11

申请号：US218384

申请日：1988-07-13

申请人： Steven L. Bard ,  Claudius Feger ,  John J. Glenning ,  Gareth G. Hougham ,  Steven E. Molis ,  Walter P. Pawlowski ,  John J. Ritsko ,  Peter Slota, Jr. ,  Randy W. Snyder

发明人： Steven L. Bard ,  Claudius Feger ,  John J. Glenning ,  Gareth G. Hougham ,  Steven E. Molis ,  Walter P. Pawlowski ,  John J. Ritsko ,  Peter Slota, Jr. ,  Randy W. Snyder

IPC分类号： G03F7/26 ,  C08J7/12 ,  G03F7/40 ,  H01L21/306 ,  H01L21/311 ,  H05K1/03 ,  H05K3/00 ,  H05K3/10

CPC分类号： C08J7/12 ,  H01L21/31133 ,  H05K3/002 ,  C08J2379/08 ,  H05K1/0346 ,  H05K2201/0154 ,  H05K2203/0793 ,  H05K3/108

摘要： Polyimide is etched by contacting the polyimide with an aqueous solution of a metal hydroxide followed by contact with an acid followed by contact with an aqueous solution of a metal hydroxide. Etching of chemically cured polyimide can be enhanced by employing a presoaking in hot water. Also, partially etched chemically cured polyimide is removed with a concentrated acid solution.In preparing a metal coated polyimide structure for subsequent gold plating, two flash etching steps with the polyimide etch between are employed after developing the photoresist.

公开(公告)号：US20130062757A1

公开(公告)日：2013-03-14

申请号：US13231594

申请日：2011-09-13

申请人： Claudius Feger ,  Michael A. Gaynes ,  Jae-Woong Nah ,  Da-Yuan Shih

发明人： Claudius Feger ,  Michael A. Gaynes ,  Jae-Woong Nah ,  Da-Yuan Shih

IPC分类号： H01L23/498 ,  H01L21/50

CPC分类号： H01L24/81 ,  H01L21/463 ,  H01L21/563 ,  H01L23/49816 ,  H01L23/544 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/743 ,  H01L24/83 ,  H01L24/92 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2223/54486 ,  H01L2224/11462 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/1605 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/2741 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/814 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2924/01029 ,  H01L2924/10253 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2224/27 ,  H01L2224/81 ,  H01L2224/83

摘要： A preassembly semiconductor device comprises substrate soldering structures extending toward chip soldering structures for forming solder connections with the chip soldering structures, i.e., the chip and the substrate are in preassembly positions relative to one another. The height of the substrate soldering structures is greater than the height of the chip soldering structures. A pre-applied underfill is contiguous with the substrate and is sufficiently thick so as to extend substantially no further than the full height of the substrate soldering structures. In another embodiment the height of the chip soldering structures is greater than the height of the substrate soldering structures and the pre-applied underfill is contiguous with the semiconductor chip and sufficiently thick so as to extend substantially no further than the full height of the chip soldering structures. A process comprises manufacturing semiconductor assemblies from these devices by soldering the semiconductor chip and the substrate to one another.

摘要翻译： 预组装半导体器件包括朝向芯片焊接结构延伸的衬底焊接结构，用于形成与芯片焊接结构的焊接连接，即，芯片和衬底相对于彼此处于预组装位置。 基板焊接结构的高度大于芯片焊接结构的高度。 预先施加的底部填充物与基底相邻并且足够厚以便基本上不超过基底焊接结构的全高度延伸。 在另一个实施例中，芯片焊接结构的高度大于衬底焊接结构的高度，并且预先施加的底部填充物与半导体芯片邻接并且足够厚以便基本上不超过芯片焊接的全部高度 结构。 一种方法包括通过将半导体芯片和衬底相互焊接来从这些器件制造半导体组件。

公开(公告)号：US20120305633A1

公开(公告)日：2012-12-06

申请号：US13154412

申请日：2011-06-06

申请人： Claudius Feger ,  Mark H. McLeod ,  Jae-Woong Nah ,  Eric D. Perfecto

发明人： Claudius Feger ,  Mark H. McLeod ,  Jae-Woong Nah ,  Eric D. Perfecto

IPC分类号： B23K1/20 ,  B23K31/02

CPC分类号： B23K1/0016 ,  B23K1/20 ,  B23K3/0623 ,  B23K2101/42 ,  H01L21/6835 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2221/68372 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/11002 ,  H01L2224/11312 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/11902 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1403 ,  H01L2224/14505 ,  H01L2224/16237 ,  H01L2224/94 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01083 ,  H01L2924/01049 ,  H01L2924/01079 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/81805

摘要： Solder bumps of uniform height are provided on a substrate through the use of injection molded solder. Copper pillars or ball limiting metallurgy are formed over I/O pads within the channels of a patterned layer of photoresist. Solder is injected over the pillars or BLM, filling the channels. The solder, which does not contain flux, is allowed to solidify. It forms a plurality of solder structures (bumps) of equal heights. Solder injection and solidification are preferably carried out in a nitrogen environment or a forming gas environment. Molten solder can be injected in channels formed in round wafers without spillage using a carrier assembly that accommodates such wafers and a fill head.

公开(公告)号：US07951648B2

公开(公告)日：2011-05-31

申请号：US12166286

申请日：2008-07-01

申请人： Claudius Feger ,  Nancy LaBianca

发明人： Claudius Feger ,  Nancy LaBianca

IPC分类号： H01L21/44

CPC分类号： H01L21/563 ,  H01L23/544 ,  H01L24/29 ,  H01L24/75 ,  H01L24/81 ,  H01L2223/54426 ,  H01L2223/5448 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/274 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81121 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/83191 ,  H01L2224/83194 ,  H01L2224/83856 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401

摘要： A process comprises forming a first electrical interconnect structure on a surface of a singulated semiconductor chip having an alignment pattern, which is scanned and stored in a scanning device prior to application of a curable underfill coating to the surface of the singulated semiconductor chip. A curable underfill coating is applied to the surface of the singulated semiconductor chip to produce a coated semiconductor chip. The scanned and stored alignment pattern is delivered to an alignment and joining device positioned adjacent to and operatively associated with a substrate having a second electrical interconnect structure alignable to make electrical contact with the first electrical interconnect structure. The coated semiconductor chip is placed in the alignment and joining device so that when the scanned and stored alignment pattern is activated the alignment and joining device positions the coated semiconductor chip so that the first electrical interconnect structure is aligned to make electrical contact with the second electrical interconnect structure. The alignment and joining device is activated to join the coated semiconductor chip to the substrate.

摘要翻译： 一种方法包括在具有对准图案的单片化半导体芯片的表面上形成第一电互连结构，其在将可固化底部填充涂层施加到单片化半导体芯片的表面之前被扫描并存储在扫描装置中。 将可固化的底部填充涂层施加到单片半导体芯片的表面，以制造涂覆的半导体芯片。 扫描和存储的对准图案被传送到与基板相邻并且可操作地与具有可与第一电互连结构电接触的第二电互连结构的基板定位的对准和接合装置。 涂覆的半导体芯片被放置在对准和接合装置中，使得当扫描和存储的对准图案被激活时，对准和接合装置将涂覆的半导体芯片定位，使得第一电互连结构对准以与第二电气 互连结构。 激活对准和接合装置以将涂覆的半导体芯片连接到基板。

公开(公告)号：US07516674B1

公开(公告)日：2009-04-14

申请号：US12198479

申请日：2008-08-26

申请人： Claudius Feger ,  Soojae Park

发明人： Claudius Feger ,  Soojae Park

IPC分类号： G01N19/08

CPC分类号： G01N3/60 ,  G01N2203/0066 ,  G01N2203/0073 ,  G01N2203/027

摘要： A method for measuring the fracture and fatigue crack growth behavior of a material includes heating at least one sample having a first end and a second end and a pre-applied crack between the first end and the second end; heating a fixture having a lower coefficient of thermal expansion than said at least one sample; attaching the first end and the second end of the at least one sample to the fixture; cooling the at least one sample and fixture; recording the temperature at which propagation of the pre-applied crack through the width of the at least one sample occurs as the critical fracture temperature; for a plurality of samples, each sample having a different ratio of pre-applied crack length to sample width, determining the critical fracture temperature as a function of said ratio; and ranking materials by the critical fracture temperature.

摘要翻译： 用于测量材料的断裂和疲劳裂纹扩展行为的方法包括加热至少一个具有第一端和第二端的样品和在第一端和第二端之间的预应力裂纹; 加热具有比所述至少一个样品更低的热膨胀系数的固定装置; 将所述至少一个样品的第一端和第二端附接到所述夹具; 冷却至少一个样品和固定装置; 记录预先施加的裂纹的传播通过至少一个样品的宽度的温度作为临界断裂温度; 对于多个样品，每个样品具有不同的预先施加的裂纹长度与样品宽度的比率，确定临界裂纹温度作为所述比例的函数; 并按临界断裂温度对材料进行排序。

公开(公告)号：US20090080833A1

公开(公告)日：2009-03-26

申请号：US12189143

申请日：2008-08-09

申请人： Claudius Feger ,  Philip O. D. Hobbs ,  Maurice McGlashan-Powell

发明人： Claudius Feger ,  Philip O. D. Hobbs ,  Maurice McGlashan-Powell

IPC分类号： G02B6/26 ,  G02B6/02 ,  G02B6/36

CPC分类号： G02B6/2821 ,  G02B6/02 ,  G02B6/02033 ,  G02B6/03622 ,  G02B6/283 ,  G02B6/29316 ,  G02B6/421 ,  G02B6/4249

摘要： A single-mode optical waveguide with a core, surrounded by a cladding consisting of an inner soft layer and an outer harder layer is described. The outer layer has a grating structure on its inner surface, whose spatial frequency is the same as that of the guided mode. The thickness of the inner cladding is sufficient to keep the grating outside the mode field in undeformed regions of the waveguide, so that normally no out-coupling of the light results. Connections are made by crossing two such waveguides at an angle and pressing them together. This results in deformation of the two waveguides such that the gratings are brought into proximity with the cores. Light is coupled out of one waveguide and into the other in the deformed region, resulting in a self-aligning optical connection. The out-coupled light propagates normal to the waveguide axis, so errors in the crossing angle cause little change in efficiency. Because the cladding system is sufficiently resilient to recover after deformation, the connection is remakeable.

摘要翻译： 描述了具有由包含内软层和外硬层的覆层围绕的芯的单模光波导。 外层在其内表面具有光栅结构，其空间频率与导向模式相同。 内包层的厚度足以将光栅保持在波导的未变形区域中的模场外，使得通常不会导致光的外耦合。 通过将两个这样的波导以一定角度交叉并将它们压在一起而形成连接。 这导致两个波导的变形，使得光栅与芯接近。 光从一个波导耦合到变形区域中的另一个，导致自对准光学连接。 输出耦合光垂直于波导轴传播，因此交叉角的误差几乎不会导致效率的变化。 因为包层系统具有足够的弹性以在变形后恢复，所以连接是可重新制造的。

公开(公告)号：US20080284052A1

公开(公告)日：2008-11-20

申请号：US11750559

申请日：2007-05-18

申请人： Claudius Feger ,  Ijeoma M. Nnebe ,  Maurice McGlashan-Powell

发明人： Claudius Feger ,  Ijeoma M. Nnebe ,  Maurice McGlashan-Powell

IPC分类号： B29C47/76 ,  B29C47/38

CPC分类号： B29C47/76 ,  B22F3/20 ,  B22F2003/208 ,  B23K35/025 ,  B29C47/0009 ,  B29C47/38 ,  B29C47/82 ,  B29C47/822 ,  B29C47/825 ,  B29C47/827 ,  H01L23/42 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a thermal paste, in which the method includes feeding the thermal paste into a chamber of an extruder; mixing the thermal paste at elevated temperatures; de-airing the thermal paste; and extruding the thermal paste out of the chamber through a die as a pre-form or into a cartridge, such that air channels and pseudo-grain boundaries are prevented from forming in the thermal paste.

摘要翻译： 一种制造热糊料的方法，其中该方法包括将热糊料进料到挤出机的室中; 在高温下混合热膏; 放热加热膏; 并且通过作为预成型体的模具或者进入筒体，将所述热膏料挤出所述腔室，从而防止在所述热浆料中形成空气通道和假晶粒边界。

公开(公告)号：US20080265445A1

公开(公告)日：2008-10-30

申请号：US11742200

申请日：2007-04-30

申请人： Claudius Feger ,  Nancy LaBianca

发明人： Claudius Feger ,  Nancy LaBianca

IPC分类号： H01L21/58 ,  H01L23/544

CPC分类号： H01L23/544 ,  H01L21/563 ,  H01L21/78 ,  H01L24/11 ,  H01L24/29 ,  H01L24/81 ,  H01L24/94 ,  H01L2223/54413 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2223/5448 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/274 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81121 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/83191 ,  H01L2224/83856 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01076 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/0401

摘要： A semiconductor wafer and the process for aligning wafer level underfill material coated chips with a substrate via alignment marks made visible through laser dicing.

摘要翻译： 半导体晶片和通过激光切割可见的对准标记将经晶片级底层填充材料涂覆的芯片与基板对准的工艺。

公开(公告)号：US20080220998A1

公开(公告)日：2008-09-11

申请号：US11683825

申请日：2007-03-08

申请人： Claudius Feger ,  Jeffrey D. Gelorme ,  Sushumna Iruvanti ,  Rajneesh Kumar ,  Ijeoma M. Nnebe

发明人： Claudius Feger ,  Jeffrey D. Gelorme ,  Sushumna Iruvanti ,  Rajneesh Kumar ,  Ijeoma M. Nnebe

IPC分类号： C10M101/04 ,  H01L23/34

CPC分类号： H01L23/3737 ,  C10M169/02 ,  C10M171/02 ,  C10M2201/0413 ,  C10M2201/053 ,  C10M2201/0613 ,  C10M2201/0623 ,  C10M2201/1006 ,  C10M2201/1023 ,  C10M2203/1025 ,  C10M2203/1045 ,  C10M2205/02 ,  C10M2205/04 ,  C10M2207/401 ,  C10M2209/084 ,  C10M2209/102 ,  C10M2209/103 ,  C10M2209/1033 ,  C10M2211/083 ,  C10M2217/044 ,  C10M2229/02 ,  C10M2229/025 ,  C10N2220/00 ,  C10N2220/082 ,  C10N2220/084 ,  C10N2220/086 ,  C10N2230/00 ,  C10N2230/02 ,  C10N2230/08 ,  C10N2240/20 ,  C10N2250/18 ,  H01L2924/0002 ,  H01L2924/00

摘要： A reversible thermal thickening grease for microelectronic packages, in which the grease contains filler particles; at least one polymer; and a binder; in which the filler particles are dispersed within the binder, in which one or more segments of the at least one polymer may be attached to the filler particles prior to dispersion in the binder, and in which the polymer collapses at temperatures below a Theta temperature and swells at temperatures above a Theta temperature. During the operation of a microelectronic package, grease pump-out and air proliferation are minimized with use of the reversible thermal thickening grease, while grease fluidity is retained under repetitive thermal stresses.

摘要翻译： 用于微电子封装的可逆热增稠润滑脂，其中润滑脂含有填料颗粒; 至少一种聚合物; 和粘合剂; 其中所述填料颗粒分散在所述粘合剂内，其中所述至少一种聚合物的一个或多个链段可以在分散在所述粘合剂中之前附着到所述填料颗粒上，并且其中所述聚合物在低于所述陶瓷温度的温度下塌陷， 在高于Theta温度的温度下膨胀。 在微电子封装的运行过程中，使用可逆的热增稠润滑脂使润滑脂泵出和空气扩散最小化，同时在重复的热应力下保持润滑脂的流动性。