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54 条记录 (耗时 0.038 秒)

    Circuit package having low modulus, conformal mounting pads
    42.
    发明授权
    Circuit package having low modulus, conformal mounting pads 失效
    具有低模数，适形安装垫的电路封装

    公开(公告)号：US06399896B1

    公开(公告)日：2002-06-04

    申请号：US09525379

    申请日：2000-03-15

    申请人： Frank J. Downes, Jr. ,  Donald S. Farquhar ,  Robert M. Japp ,  William J. Rudik

    发明人： Frank J. Downes, Jr. ,  Donald S. Farquhar ,  Robert M. Japp ,  William J. Rudik

    IPC分类号： H05K116

    CPC分类号： H05K3/326 ,  H05K1/0271 ,  H05K1/111 ,  H05K1/114 ,  H05K2201/0133 ,  H05K2201/0187 ,  H05K2201/10734 ,  H05K2203/0307

    摘要： Reliability of circuit packaging while accommodating larger chips and increased temperature excursions is achieved by use of compliant pads only at the locations of connections between packaging levels, preferably between a laminated chip carrier and a printed circuit board. The invention allows the coefficient of thermal expansion of the chip carrier to be economically well-matched to the CTE of the chip and accommodation of significant differences in CTEs of package materials to be accommodated at a single packaging level. The compliant pads are preferably of low aspect ratio which are not significantly deflected by accelerations and can be formed on a surface or recessed into it. Connections can be made through surface connections and/or plated through holes. Connection enhancements such as solder wettable surfaces or dendritic textures are provided in a conductive metal or alloy layer over a compliant rubber or elastomer layer which may be conductive or non-conductive.

    摘要翻译： 通过仅在封装层之间的连接位置（优选在层压芯片载体和印刷电路板之间）使用柔性焊盘来实现电路封装的可靠性，同时容纳更大的芯片和增加的温度漂移。 本发明允许芯片载体的热膨胀系数与芯片的CTE经济地良好匹配，并且可以容纳在单个封装层面上容纳的封装材料的CTE的显着差异。 柔性衬垫优选地具有低纵横比，其不被加速度显着偏转，并且可以形成在表面上或凹入其中。 可以通过表面连接和/或电镀通孔进行连接。 在导电金属或合金层中的柔性橡胶或弹性体层上提供诸如焊料可润湿表面或树枝状织构的连接增强，其可以是导电的或不导电的。

    Z-interconnections with liquid crystal polymer dielectric films
    46.
    发明授权
    Z-interconnections with liquid crystal polymer dielectric films 失效
    与液晶聚合物电介质薄膜的Z互连

    公开(公告)号：US07128256B2

    公开(公告)日：2006-10-31

    申请号：US10813411

    申请日：2004-03-30

    申请人： Donald S. Farquhar ,  Douglas O. Powell

    发明人： Donald S. Farquhar ,  Douglas O. Powell

    IPC分类号： B23K31/00

    CPC分类号： H05K3/4617 ,  B32B27/36 ,  H05K3/4688 ,  H05K2201/0141 ,  Y10S428/901 ,  Y10T29/49117 ,  Y10T156/1052 ,  Y10T428/24917

    摘要： A multilayered stack and method of formation. First and second dielectric layers are formed, respectively including first and second liquid crystal polymer (LCP) dielectric materials, with an electrically conductive plug through the first dielectric layer. A first and second electrical circuitization is formed in direct mechanical contact with a surface of the first and second dielectric layer, respectively, wherein the second electrical circuitization mechanically and electrically contacts an end of the plug, and wherein the plug is fluxlessly soldered to the first electrical circuitization. The first and second dielectric layers and the first electrical circuitization are subjected to a temperature below the lowest nematic-to-isotropic transition temperature of the first and second LCP dielectric materials, for a dwell time and elevated pressure sufficient to cause the first and second LCP dielectric materials to directly bond the second dielectric layer to the first dielectric layer and to the first electrical circuitization.

    摘要翻译： 多层堆叠和形成方法。 形成第一和第二电介质层，分别包括第一和第二液晶聚合物（LCP）电介质材料，其具有通过第一介电层的导电插塞。 第一和第二电气电路分别形成为与第一和第二介电层的表面直接机械接触，其中第二电路机械地和电接触插头的端部，并且其中插头被无焊焊接到第一 电气化。 第一和第二电介质层和第一电路经受低于第一和第二LCP电介质材料的最低向列 - 全向转变温度的温度，停留时间和升高的压力足以引起第一和第二LCP 电介质材料，以将第二电介质层直接接合到第一电介质层和第一电路。

    Method of making a printed circuit board having filled holes and a fill member for use therewith including reinforcement means
    50.
    发明授权
    Method of making a printed circuit board having filled holes and a fill member for use therewith including reinforcement means 失效
    制造具有填充孔的印刷电路板和用于其的填充构件的方法，包括加强装置

    公开(公告)号：US06609296B1

    公开(公告)日：2003-08-26

    申请号：US09562580

    申请日：2000-05-01

    申请人： Donald S. Farquhar ,  Voya R. Markovich ,  Kostas I. Papathomas ,  Leonard L. Schmidt

    发明人： Donald S. Farquhar ,  Voya R. Markovich ,  Kostas I. Papathomas ,  Leonard L. Schmidt

    IPC分类号： H01K310

    CPC分类号： H05K3/0094 ,  H05K1/0366 ,  H05K1/113 ,  H05K3/246 ,  H05K3/4069 ,  H05K2201/0347 ,  H05K2201/0959 ,  H05K2203/0278 ,  H05K2203/0338 ,  H05K2203/1453 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165

    摘要： A method of making a circuitized substrate such as a printed circuit board having at least one hole therein which comprises the steps of providing a layer of dielectric, forming at least one (and preferably several) holes therein, providing a fill member including a quantity of fill material and reinforcement means located within the fill material, positioning the fill member on the dielectric over the holes and thereafter applying a predetermined force sufficient to cause only the fill material to be forcibly driven into the accommodating hole(s), not the reinforcement means. Subsequent steps can include forming a layer of circuitry on the substrate's external surface and over the filled holes such that an electrical component such as a ball grid array (BGA), semiconductor chip, etc. may be directly positioned on and/or over the hole(s). A fill member usable with the method is also provided.

    摘要翻译： 一种制造电路化基板的方法，例如其中具有至少一个孔的印刷电路板，其包括以下步骤：提供介电层，在其中形成至少一个（并且优选几个）孔，提供填充构件，该填充构件包括一定量的 填充材料和加强装置，其位于填充材料内，将填充构件定位在电介质上的孔上，然后施加足以使填充材料被强制地驱动进入容纳孔的预定力，而不是加强装置 。 随后的步骤可以包括在衬底的外表面上和填充的孔上形成电路层，使得电子部件例如球栅阵列（BGA），半导体芯片等可以直接定位在孔的上和/或上方 （s）。 还提供了可用于该方法的填充构件。