公开(公告)号：US09165837B1

公开(公告)日：2015-10-20

申请号：US14525743

申请日：2014-10-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jody Fronheiser ,  Murat Kerem Akarvardar ,  Ajey P. Jacob ,  Steven Bentley

IPC: H01L21/336 ,  H01L21/00 ,  H01L21/20 ,  H01L21/8238 ,  H01L21/3065 ,  H01L21/762 ,  H01L21/8234

CPC classification number: H01L21/823821 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3247 ,  H01L21/76224 ,  H01L21/823431

Abstract: Methods of forming a defect free heteroepitaxial replacement fin by annealing the sacrificial Si fin with H2 prior to STI formation are provided. Embodiments include forming a Si fin on a substrate; annealing the Si fin with H2; forming a STI layer around the annealed Si fin; annealing the STI layer; removing a portion of the annealed Si fin by etching, forming a recess; forming a replacement fin in the recess; and recessing the annealed STI layer to expose an active replacement fin.

Abstract translation: 提供了在STI形成之前通过用H 2退火牺牲Si翅片来形成无缺陷异质外延替换翅片的方法。 实施例包括在基板上形成Si翅片; 用H2退火Si翅片; 在退火的Si翅片周围形成STI层; 退火STI层; 通过蚀刻去除退火的Si翅片的一部分，形成凹部; 在凹槽中形成替换翅片; 并使退火的STI层凹陷以暴露活性替换翅片。

公开(公告)号：US20150255608A1

公开(公告)日：2015-09-10

申请号：US14200952

申请日：2014-03-07

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Xiuyu Cai ,  Ruilong Xie ,  Ajey P. Jacob ,  Witold P. Maszara ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/76224 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7849 ,  H01L29/785

Abstract: One method disclosed includes, among other things, forming an initial fin structure comprised of portions of a substrate, a first epi semiconductor material and a second epi semiconductor material, forming a layer of insulating material so as to over-fill the trenches that define the fin, recessing a layer of insulating material such that a portion, but not all, of the second epi semiconductor portion of the final fin structure is exposed, forming a gate structure around the final fin structure, further recessing the layer of insulating material such that the first epi semiconductor material is exposed, removing the first epi semiconductor material to thereby define an under-fin cavity and substantially filling the under-fin cavity with a stressed material.

Abstract translation: 所公开的一种方法包括形成由衬底，第一外延半导体材料和第二外延半导体材料的部分组成的初始鳍结构，形成绝缘材料层，从而过度填充限定 翅片，使一层绝缘材料凹陷，使得最终翅片结构的第二外延半导体部分的一部分（但不是全部）暴露，围绕最终翅片结构形成栅极结构，进一步使绝缘材料层凹陷，使得 第一外延半导体材料被暴露，去除第一外延半导体材料，从而限定下鳍腔，并用受压材料基本上填充底鳍腔。

公开(公告)号：US08963259B2

公开(公告)日：2015-02-24

申请号：US13906852

申请日：2013-05-31

Applicant: GlobalFoundries Inc.

Inventor： Ajey P. Jacob ,  Murat K. Akarvardar ,  Steven J. Bentley ,  Toshiharu Nagumo ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L21/761 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L21/823821 ,  H01L21/02227 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/266 ,  H01L21/3086 ,  H01L21/761 ,  H01L21/76224 ,  H01L21/823878 ,  H01L29/0646 ,  H01L29/66795 ,  H01L29/7851

Abstract: Embodiments herein provide approaches for device isolation in a complimentary metal-oxide fin field effect transistor. Specifically, a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage. A set of replacement fins is formed over the retrograde doped layer, each of the set of replacement fins comprising a high mobility channel material (e.g., silicon, or silicon-germanium). The retrograde doped layer may be formed using an in situ doping process or a counter dopant retrograde implant. The device may further include a carbon liner positioned between the retrograde doped layer and the set of replacement fins to prevent carrier spill-out to the replacement fins.

Abstract translation: 本文的实施例提供了在互补金属氧化物鳍片场效应晶体管中的器件隔离的方法。 具体地，半导体器件在衬底上形成有逆向掺杂层以最小化源极到漏极穿通泄漏。 在逆向掺杂层上形成一组替代翅片，该组替换鳍片中的每一个包括高迁移率通道材料（例如，硅或硅 - 锗）。 逆向掺杂层可以使用原位掺杂工艺或反掺杂剂逆向植入来形成。 该装置还可以包括位于逆向掺杂层和该替代翅片组之间的碳衬垫，以防止载体溢出到置换翅片。

公开(公告)号：US20140273423A1

公开(公告)日：2014-09-18

申请号：US13798616

申请日：2013-03-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jody A. Fronheiser ,  Jeremy A. Wahl ,  Kerem Akarvardar ,  Ajey P. Jacob ,  Daniel T. Pham

IPC: H01L29/66

CPC classification number: H01L29/42392 ,  B82Y40/00 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78696

Abstract: One method disclosed herein includes forming a layer of silicon/germanium having a germanium concentration of at least 30% on a semiconducting substrate, forming a plurality of spaced-apart trenches that extend through the layer of silicon/germanium and at least partially into the semiconducting substrate, wherein the trenches define a fin structure for the device comprised of a portion of the substrate and a portion of the layer of silicon/germanium, the portion of the layer of silicon/germanium having a first cross-sectional configuration, forming a layer of insulating material in the trenches and above the fin structure, performing an anneal process on the device so as to cause the first cross-sectional configuration of the layer of silicon/germanium to change to a second cross-sectional configuration that is different from the first cross-sectional configuration, and forming a final gate structure around at least a portion of the layer of silicon/germanium having the second cross-sectional configuration.

Abstract translation: 本文公开的一种方法包括在半导体衬底上形成具有至少30％的锗浓度的硅/锗层，形成多个间隔开的沟槽，其延伸穿过硅/锗层并且至少部分地进入半导体 衬底，其中所述沟槽限定由所述衬底的一部分和所述硅/锗层的一部分组成的器件的鳍结构，所述硅/锗层的所述部分具有第一横截面构造，形成层 的绝缘材料在沟槽中并在鳍结构之上，对器件进行退火处理，以使硅/锗层的第一截面构型变为不同于第二截面结构 第一横截面构造，以及围绕具有第二横截面的硅/锗层的至少一部分形成最终栅极结构 功能配置

公开(公告)号：US10388691B2

公开(公告)日：2019-08-20

申请号：US15599427

申请日：2017-05-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Srinivasa Banna ,  Deepak Nayak ,  Ajey P. Jacob

IPC: H01L27/15 ,  H01L33/06 ,  H01L33/32 ,  H01L33/24

Abstract: A color stacked light emitting diode (LED) pixel is disclosed. The color stacked LED includes an LED pixel structure body, a base LED disposed on at least a portion of the LED pixel structure body, an intermediate LED disposed on the base LED, and a top LED disposed on the intermediate LED. The stacked LED may be an overlapping or a non-overlapping LED pixel. The LED pixel structure body may be a fin body or a nanowire body.

公开(公告)号：US10355043B2

公开(公告)日：2019-07-16

申请号：US15635608

申请日：2017-06-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ajey P. Jacob ,  Deepak K. Nayak ,  Srinivasa R. Banna

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/16 ,  H01L33/32 ,  H01L29/417 ,  H01L33/36 ,  H01L29/778 ,  H01L33/00 ,  H01L27/15 ,  H01L29/66 ,  H01L29/20 ,  H01L29/10 ,  H01L29/872

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to integrated vertical transistors and light emitting diodes and methods of manufacture. The structure includes a vertically oriented stack of material having a light emitting diode (LED) integrated with a source region and a drain region of a vertically oriented active device.

公开(公告)号：US10319642B2

公开(公告)日：2019-06-11

申请号：US15667305

申请日：2017-08-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Suraj Kumar Patil ,  Ajey P. Jacob

IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/115 ,  H01L29/788 ,  H01L27/092 ,  H01L29/49 ,  H01L21/302 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/786 ,  H01L29/423 ,  H01L21/8258

Abstract: A method of forming Si or Ge-based and III-V based vertically integrated nanowires on a single substrate and the resulting device are provided. Embodiments include forming first trenches in a Si, Ge, III-V, or SixGe1-x substrate; forming a conformal SiN, SiOxCyNz layer over side and bottom surfaces of the first trenches; filling the first trenches with SiOx; forming a first mask over portions of the Si, Ge, III-V, or SixGe1-x substrate; removing exposed portions of the Si, Ge, III-V, or SixGe1-x substrate, forming second trenches; forming III-V, III-VxMy, or Si nanowires in the second trenches; removing the first mask and forming a second mask over the III-V, III-VxMy, or Si nanowires and intervening first trenches; removing the SiOx layer, forming third trenches; and removing the second mask.

公开(公告)号：US10037981B2

公开(公告)日：2018-07-31

申请号：US15599465

申请日：2017-05-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Srinivasa Banna ,  Sanjay Jha ,  Deepak Nayak ,  Ajey P. Jacob

IPC: H01L33/00 ,  H01L25/16 ,  H01L23/48 ,  H01L25/00 ,  H01L23/00 ,  H01L25/075 ,  H01L27/15 ,  H01L33/32 ,  H01L33/06 ,  H01L33/24 ,  H01L27/092 ,  H01L21/8258 ,  H01L27/06

CPC classification number: H01L25/167 ,  H01L21/76898 ,  H01L21/8258 ,  H01L23/481 ,  H01L24/06 ,  H01L24/08 ,  H01L25/0753 ,  H01L25/50 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/156 ,  H01L33/06 ,  H01L33/24 ,  H01L33/32 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/08147

Abstract: A display system is disclosed. The display system comprises a light emitting diode (LED) device and a backplane (BP) device. The LED device comprises a plurality of LEDs having LED terminals. An LED bonding surface comprising a dielectric layer with LED bonding surface contact pads is coupled to diode terminals of the LEDs. The backplane (BP) device comprises a BP substrate having top and bottom surfaces. A plurality of system on chip (SoC) chips are bonded to chip pads disposed on a bottom surface of the BP device. The SoC chips are electrically coupled to the CMOS components of the BP device and LEDs of the LED device.

公开(公告)号：US09864136B1

公开(公告)日：2018-01-09

申请号：US15231840

申请日：2016-08-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ajey P. Jacob

IPC: G02B6/12 ,  H01L31/028 ,  H01L31/0304 ,  H01L31/12 ,  G02B6/13

CPC classification number: G02B6/12004 ,  G02B6/131 ,  G02B2006/12097 ,  G02B2006/121 ,  G02B2006/12123 ,  H01L31/028 ,  H01L31/0304 ,  H01L31/125

Abstract: Disclosed are non-planar monolithic hybrid optoelectronic structures. These structures are referred to as non-planar because they contain one or more semiconductor fins. These structures are referred to as monolithic because they contain, within each semiconductor fin, an optical waveguide core positioned laterally between a light sensor and a photodetector. Specifically, each semiconductor fin has end portions and a center portion positioned laterally between the end portions. The center portion is an optical waveguide core and the end portions have trenches that contain the light source and photodetector, respectively. These structures are referred to as hybrid because the optical waveguide core is made of one semiconductor material and the light sensor and photodetector are each made of at least one additional semiconductor material that is different from the semiconductor material of the center portion. Also disclosed herein are methods of forming monolithic non-planar hybrid optoelectronic structures.

公开(公告)号：US09842897B2

公开(公告)日：2017-12-12

申请号：US15176073

申请日：2016-06-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Murat K. Akarvardar ,  Ajey P. Jacob

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/06 ,  H01L27/02 ,  H01L21/02 ,  H01L29/165 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/762 ,  H01L29/08 ,  H01L29/161

CPC classification number: H01L29/1083 ,  H01L21/02236 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/76216 ,  H01L21/76281 ,  H01L27/0255 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A bulk finFET with partial dielectric isolation is disclosed. The dielectric isolation is disposed underneath the channel, and essentially bounded by the channel, such that it does not extend laterally beyond the channel under the source and drain regions. This allows increased volume of SiGe source and drain stressor regions placed adjacent to the channel, allowing for a more strained channel, which improves carrier mobility. An N+ doped silicon region is disposed below the dielectric isolation and extends laterally beyond the channel and underneath the stressor source and drain regions, forming a reverse-biased p/n junction with the P+ doped source and drain SiGe stressor to minimize leakage currents from under the insulator.