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    High density interconnect structures configured for manufacturing and performance
    41.
    发明授权
    High density interconnect structures configured for manufacturing and performance 有权

    公开(公告)号：US10833020B2

    公开(公告)日：2020-11-10

    申请号：US16305752

    申请日：2016-06-30

    Applicant: Intel Corporation

    Inventor： Henning Braunisch ,  Kemal Aygun ,  Ajay Jain ,  Zhiguo Qian

    IPC: H01L21/48 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L23/14 ,  H01L23/31

    Abstract: Discussed generally herein are methods and devices including or providing a high density interconnect structure. A high density interconnect structure can include a stack of alternating dielectric layers and metallization layers comprising at least three metallization layers including conductive material with low k dielectric material between the conductive material, and at least two dielectric layers including first medium k dielectric material with one or more first vias extending therethrough, the at least two dielectric layers situated between two metallization layers of the at least three metallization layers, a second medium k dielectric material directly on a top surface of the stack, a second via extending through the second medium k dielectric material, the second via electrically connected to conductive material in a metallization layer of the three or more metallization layers, and a pad over the second medium k dielectric material and electrically connected to the second via.

    Package substrates with magnetic build-up layers
    43.
    发明授权
    Package substrates with magnetic build-up layers 有权

    公开(公告)号：US10748842B2

    公开(公告)日：2020-08-18

    申请号：US15926531

    申请日：2018-03-20

    Applicant: Intel Corporation

    Inventor： Zhiguo Qian ,  Kaladhar Radhakrishnan ,  Kemal Aygun

    IPC: H01L23/49 ,  H01L23/498 ,  H01L21/68 ,  H01L21/48 ,  H01L23/00

    Abstract: The present disclosure is directed to systems and methods for improving the impedance matching of semiconductor package substrates by incorporating one or more magnetic build-up layers proximate relatively large diameter, relatively high capacitance, conductive pads formed on the lower surface of the semiconductor package substrate. The one or more magnetic layers may be formed using a magnetic build-up material deposited on the lower surface of the semiconductor package substrate. Vias conductively coupling the conductive pads to bump pads on the upper surface of the semiconductor package substrate pass through and are at least partially surrounded by the magnetic build-up material.

    Shielded bundle interconnect
    47.
    发明申请
    Shielded bundle interconnect 审中-公开

    公开(公告)号：US20170187419A1

    公开(公告)日：2017-06-29

    申请号：US14998254

    申请日：2015-12-26

    Applicant: Intel Corporation

    Inventor： Yu Zhang ,  Mathew J. Manusharow ,  Adel A. Elsherbini ,  Henning Braunisch ,  Kemal Aygun

    IPC: H04B3/32 ,  H04L5/14

    CPC classification number: H04B3/32 ,  H01L2224/16225 ,  H01L2924/15192 ,  H01L2924/15311

    Abstract: Embodiments are generally directed to a shielded bundle interconnect. An embodiment of an apparatus includes multiple signal bundles, the signal bundles including a first signal bundle including a first plurality of signals and a second signal bundle including a second plurality of signals; and a lithographic via shielding to provide electromagnetic shielding, the lithographic via shielding located at least in part between the first signal bundle and the second signal bundle, wherein the lithographic via shielding includes at least a via generated by a lithographic via process. The lithographic via shielding partially or completely surrounds at least one of the signal bundles of the apparatus.

    INDUCTORS FOR CIRCUIT BOARD THROUGH HOLE STRUCTURES
    48.
    发明申请
    INDUCTORS FOR CIRCUIT BOARD THROUGH HOLE STRUCTURES 有权
    电路板通过孔结构的电感器

    公开(公告)号：US20160276092A1

    公开(公告)日：2016-09-22

    申请号：US14678714

    申请日：2015-04-03

    Applicant: Intel Corporation

    Inventor： Zhichao Zhang ,  Gong Ouyang ,  Kai Xiao ,  Kemal Aygun ,  Beom-Taek Lee

    IPC: H01F27/28 ,  H05K1/18 ,  H05K1/02 ,  H05K1/11

    CPC classification number: H05K1/0237 ,  H01F17/0013 ,  H01F2017/002 ,  H05K1/0233 ,  H05K1/116 ,  H05K1/165

    Abstract: Systems, apparatuses, and methods may include a circuit board having a plated through hole with a via portion and a stub portion and a self-coupled inductor electrically coupled to the via portion of the plated through hole. The self-coupled inductor may include a first inductor mutually coupled to a second inductor in series to reduce a capacitive effect of the stub portion of the plated through hole.

    Abstract translation: 系统，装置和方法可以包括具有电镀通孔的电路板，其具有通孔部分和短截线部分，以及电耦合到电镀通孔的通孔部分的自耦合电感器。 自耦合电感器可以包括串联耦合到第二电感器的第一电感器，以减小电镀通孔的短截线部分的电容效应。

    INTERCONNECT ROUTING CONFIGURATIONS AND ASSOCIATED TECHNIQUES
    49.
    发明申请
    INTERCONNECT ROUTING CONFIGURATIONS AND ASSOCIATED TECHNIQUES 有权
    互连路由配置和相关技术

    公开(公告)号：US20160085899A1

    公开(公告)日：2016-03-24

    申请号：US14491693

    申请日：2014-09-19

    Applicant: Intel Corporation

    Inventor： Zhiguo Qian ,  Kemal Aygun ,  Dae-Woo Kim

    IPC: G06F17/50 ,  H01L23/00 ,  H01L21/768 ,  H01L23/538

    CPC classification number: H01L23/5381 ,  G06F17/5077 ,  H01L21/4857 ,  H01L21/76802 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/15311

    Abstract: Embodiments of the present disclosure are directed toward interconnect routing configurations and associated techniques. In one embodiment, an apparatus includes a substrate, a first routing layer disposed on the substrate and having a first plurality of traces, and a second routing layer disposed directly adjacent to the first routing layer and having a second plurality of traces, wherein a first trace of the first plurality of traces has a width that is greater than a width of a second trace of the second plurality of traces. Other embodiments may be described and/or claimed.

    Abstract translation: 本公开的实施例涉及互连路由配置和相关技术。 在一个实施例中，一种装置包括基板，设置在基板上并具有第一多个迹线的第一布线层和与第一布线层直接相邻设置且具有第二多个迹线的第二布线层，其中第一布线层 第一多个迹线的迹线具有大于第二多个迹线的第二迹线的宽度的宽度。 可以描述和/或要求保护其他实施例。

    Ground via clustering for crosstalk mitigation
    50.
    发明授权
    Ground via clustering for crosstalk mitigation 有权

    公开(公告)号：US09230900B1

    公开(公告)日：2016-01-05

    申请号：US14575956

    申请日：2014-12-18

    Applicant: Intel Corporation

    Inventor： Zhiguo Qian ,  Kemal Aygun ,  Yu Zhang

    IPC: H01L23/52 ,  H01L23/498

    CPC classification number: H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311

    Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.

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