公开(公告)号：US20200312787A1

公开(公告)日：2020-10-01

申请号：US16369681

申请日：2019-03-29

申请人： Intel Corporation

发明人： Yonggang Li ,  Brandon C. Marin ,  Vahidreza Parichehreh ,  Jeremy D. Ecton

IPC分类号： H01L23/00 ,  H01L23/498 ,  H01L23/14 ,  H01L21/48

摘要： A package for an electronic device may include a first layer. The first layer may include a first dielectric material. The first layer may have a planar first surface. The first layer may have a variable thickness. A second layer may be coupled to the first layer. The second layer may include a second dielectric material and may have a planar second surface. The second layer may have a variable thickness. A seam may be located at an interface between the first layer and the second layer, and the seam may have an undulating profile. The package may include at least one electrical trace, for example located in the first layer or the second layer.

公开(公告)号：US20200253037A1

公开(公告)日：2020-08-06

申请号：US16268813

申请日：2019-02-06

申请人： Intel Corporation

发明人： Brandon C. Marin ,  Andrew James Brown ,  Rahul Jain ,  Dilan Seneviratne ,  Praneeth Kumar Akkinepally ,  Frank Truong

IPC分类号： H05K1/02 ,  H05K1/11 ,  H01L23/498

摘要： Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a substrate layer having a surface, wherein the substrate layer includes a photo-imageable dielectric (PID) and an electroless catalyst; a first conductive trace having a first thickness on the surface of the substrate layer; and a second conductive trace having a second thickness on the surface of the substrate layer, wherein the first thickness is greater than the second thickness.

公开(公告)号：US20240222257A1

公开(公告)日：2024-07-04

申请号：US18089801

申请日：2022-12-28

申请人： Intel Corporation

发明人： Bohan Shan ,  Haobo Chen ,  Srinivas Venkata Ramanuja Pietambaram ,  Hongxia Feng ,  Gang Duan ,  Xiaoying Guo ,  Yiqun Bai ,  Dingying Xu ,  Bai Nie ,  Kyle Jordan Arrington ,  Ziyin Lin ,  Rahul N. Manepalli ,  Brandon C. Marin ,  Jeremy D. Ecton

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L23/538

CPC分类号： H01L23/49894 ,  H01L21/481 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/5384 ,  H01L23/15

摘要： A substrate for an electronic system includes a glass core layer. The glass core layer includes a first surface and a second surface opposite the first surface; and at least one through-glass via (TGV) extending through the glass core layer from the first surface to the second surface. The TGV includes an opening filled with an electrically conductive material; and a via liner including a sidewall material disposed on a sidewall of the opening between the glass of the glass core layer and the electrically conductive material, wherein the sidewall material includes carbon.

公开(公告)号：US20240213170A1

公开(公告)日：2024-06-27

申请号：US18086293

申请日：2022-12-21

申请人： Intel Corporation

发明人： Bohan Shan ,  Haobo Chen ,  Yiqun Bai ,  Dingying Xu ,  Srinivas Venkata Ramanuja Pietambaram ,  Hongxia Feng ,  Gang Duan ,  Xiaoying Guo ,  Ziyin Lin ,  Bai Nie ,  Kyle Jordan Arrington ,  Jeremy D. Ecton ,  Brandon C. Marin

IPC分类号： H01L23/538 ,  H01L23/498 ,  H01L25/16 ,  H01L25/18 ,  H10B80/00

CPC分类号： H01L23/5389 ,  H01L23/49816 ,  H01L23/5386 ,  H01L25/16 ,  H01L25/18 ,  H10B80/00 ,  H01L24/13

摘要： An electronic system includes a substrate and a top surface active component die. The substrate includes a glass core layer having a glass core layer active component die disposed in a cavity and a discrete passive component disposed in another cavity; a mold layer including a mold layer active component die disposed in the mold layer; and a buildup layer contacting a top surface of the glass core layer and a bottom surface of the mold layer. The buildup layer includes electrically conductive interconnect connecting the glass core layer active component die, the discrete passive component, and the mold layer active component die. The top surface of the component die is electrically connected to the mold layer active component die.

公开(公告)号：US20240128247A1

公开(公告)日：2024-04-18

申请号：US18046635

申请日：2022-10-14

申请人： Intel Corporation

发明人： Brandon C. Marin ,  Kristof Kuwawi Darmawikarta ,  Srinivas V. Pietambaram ,  Gang Duan ,  Jeremy Ecton ,  Suddhasattwa Nad ,  Hiroki Tanaka

IPC分类号： H01L25/16 ,  H01F27/02 ,  H01F27/28 ,  H01F27/29 ,  H01F41/00 ,  H01F41/04 ,  H01L21/48 ,  H01L23/00 ,  H01L23/538

CPC分类号： H01L25/16 ,  H01F27/022 ,  H01F27/2804 ,  H01F27/292 ,  H01F41/005 ,  H01F41/041 ,  H01L21/486 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/16 ,  H01L21/4853 ,  H01L2224/16235 ,  H01L2224/16267 ,  H01L2924/19042 ,  H01L2924/19103

摘要： Embodiments described herein enable a microelectronic assembly that includes: a first substrate comprising glass and at least one inductor, the first substrate having a first side and an opposing second side; a second substrate coupled to the first side of the first substrate; and a plurality of integrated circuit (IC) dies. A first subset of the plurality of IC dies is directly coupled to the second side of the first substrate, a second subset of the plurality of IC dies is directly coupled to the second substrate adjacent to the first substrate, and a third subset of the plurality of IC dies is embedded in the second substrate between the first substrate and the second subset of the plurality of IC dies.

公开(公告)号：US20240120305A1

公开(公告)日：2024-04-11

申请号：US17938784

申请日：2022-10-07

申请人： Intel Corporation

发明人： Jeremy Ecton ,  Brandon C. Marin ,  Suddhasattwa Nad ,  Srinivas V. Pietambaram ,  Mohammad Mamunur Rahman

IPC分类号： H01L23/00 ,  H01L23/538

CPC分类号： H01L24/16 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5384 ,  H01L24/14 ,  H01L24/32 ,  H01L24/73 ,  H01L24/13 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1357 ,  H01L2224/13686 ,  H01L2224/1403 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

摘要： Embodiments of a microelectronic assembly includes: a package substrate and an integrated circuit (IC) die coupled to a surface of the package substrate by first interconnects and second interconnects, the first interconnects and the second interconnects comprising solder. The first interconnects are larger than the second interconnects, the first interconnects and the second interconnects further comprise bumps on the IC die and bond-pads on the surface of the package substrate, with the solder coupled to the bumps and the bond-pads, lateral sides of the bumps have a coating of a material that prevents solder wicking, and the surface of the package substrate includes insulative baffles between the bond-pads.

公开(公告)号：US20240113158A1

公开(公告)日：2024-04-04

申请号：US17957003

申请日：2022-09-30

申请人： Intel Corporation

发明人： Jeremy D. Ecton ,  Brandon C. Marin ,  Haobo Chen ,  Changhua Liu ,  Srinivas Venkata Ramanuja Pietambaram

IPC分类号： H01L49/02 ,  H01L25/16

CPC分类号： H01L28/91 ,  H01L25/16 ,  H01L28/92

摘要： Disclosed herein are microelectronics package architectures utilizing in-situ high surface area capacitor in substrate packages and methods of manufacturing the same. The substrates may include an anode material, a cathode material, and a conductive material. The anode material may have an anode surface that may define a plurality of anode peaks and anode valleys. The cathode material may have a cathode surface that may define a plurality of cathode peaks and cathode valleys complementary to the plurality of anode peaks and anode valleys. The conductive material may be located at the anode peaks.

公开(公告)号：US20240113047A1

公开(公告)日：2024-04-04

申请号：US17957225

申请日：2022-09-30

申请人： Intel Corporation

发明人： Srinivasan Raman ,  Brandon C. Marin ,  Suddhasattwa Nad ,  Gang Duan ,  Benjamin Duong ,  Srinivas Venkata Ramanuja Pietambaram ,  Kripa Chauhan

IPC分类号： H01L23/64

CPC分类号： H01L23/647 ,  H01L21/31105

摘要： Various embodiments disclosed relate to embedded components in glass core layers for semiconductor assemblies. The present disclosure includes a semiconductor assembly with a glass core having one or more cavities and a component embedded into the glass core at the one or more cavities portion, the component at least partially embedded in the glass core, and a semiconductor die attached to the substrate.

公开(公告)号：US20240006299A1

公开(公告)日：2024-01-04

申请号：US17855568

申请日：2022-06-30

申请人： Intel Corporation

发明人： Suddhasattwa Nad ,  Jason Steill ,  Yi Yang ,  Brandon C. Marin ,  Srinivas Venkata Ramanuja Pietambaram ,  Marcel Arlan Wall ,  Gang Duan ,  Jeremy D. Ecton

IPC分类号： H01L23/498 ,  H01L21/48

CPC分类号： H01L23/49894 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/49833 ,  H01L23/49822 ,  H01L21/4857

摘要： Disclosed herein are microelectronics package architectures utilizing SiNx based surface finishes and methods of manufacturing the same. The microelectronics packages may include a core material, a first plurality of pads, and a silicon nitride layer. The first plurality of pads are attached to the core material. The silicon nitride layer is attached to the core material. The silicon nitride material defines respective openings to expose at least a portion of each of the first plurality of pads.

公开(公告)号：US20230345621A1

公开(公告)日：2023-10-26

申请号：US18344944

申请日：2023-06-30

申请人： Intel Corporation

发明人： Brandon C. Marin ,  Andrew James Brown ,  Rahul Jain ,  Dilan Seneviratne ,  Praneeth Kumar Akkinepally ,  Frank Truong

IPC分类号： H05K1/02 ,  H01L23/498 ,  H05K1/11 ,  H05K1/18

CPC分类号： H05K1/0228 ,  H01L23/49822 ,  H05K1/0298 ,  H05K1/115 ,  H05K1/111 ,  H05K1/181

摘要： Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a dielectric layer, in a substrate, the dielectric layer including an electroless catalyst, wherein the electroless catalyst includes one or more of palladium, gold, silver, ruthenium, cobalt, copper, nickel, titanium, aluminum, lead, silicon, and tantalum; a first conductive trace having a first thickness in the dielectric layer, wherein the first thickness is between 4 um and 143 um; and a second conductive trace having a second thickness in the dielectric layer, wherein the second thickness is between 2 um and 141 um, wherein the first thickness is greater than the second thickness, and wherein the first conductive trace and the second conductive trace have sloped sidewalls.