公开(公告)号：US20240332322A1

公开(公告)日：2024-10-03

申请号：US18129407

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Srinivasan Raman ,  Brandon C. Marin ,  Srinivas Venkata Ramanuja Pietambaram ,  Gang Duan ,  Suddhasattwa Nad ,  Kripa Chauhan

IPC: H01L27/13 ,  H01L21/84 ,  H01L23/482 ,  H01L25/16 ,  H01L25/18 ,  H01L29/66 ,  H01L29/772

CPC classification number: H01L27/13 ,  H01L21/84 ,  H01L23/482 ,  H01L25/16 ,  H01L25/18 ,  H01L29/66409 ,  H01L29/772

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes an electronic package substrate including a glass core layer and a regulator circuit. A first portion of the circuit components of the regulator circuit is embedded in the glass core layer and a second portion of the circuit components of the regulator circuit is formed on a surface of the glass core layer.

公开(公告)号：US20240178207A1

公开(公告)日：2024-05-30

申请号：US18059089

申请日：2022-11-28

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Brandon C. Marin ,  Srinivas V. Pietambaram ,  Gang Duan ,  Suddhasattwa Nad

IPC: H01L25/16 ,  G02B6/42 ,  H01L23/00 ,  H01L23/15 ,  H01L23/498

CPC classification number: H01L25/167 ,  G02B6/4259 ,  G02B6/426 ,  G02B6/428 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L24/08 ,  H01L2224/08121 ,  H01L2224/08225 ,  H01L2924/1903

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a photonic assembly may include an interposer having a surface, wherein a material of the interposer includes glass and the interposer includes through-glass vias (TGVs); a photonic integrated circuit (PIC) optically coupled to the surface of the interposer by optical glue or fusion bonding and electrically coupled to the TGVs in the interposer by hybrid bond interconnects; and an optical component optically coupled to the interposer, wherein the optical component is optically coupled to the PIC by an optical pathway through the interposer.

公开(公告)号：US20240162158A1

公开(公告)日：2024-05-16

申请号：US18055605

申请日：2022-11-15

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Gang Duan ,  Jeremy Ecton ,  Sashi Shekhar Kandanur ,  Ravindranath Vithal Mahajan ,  Suddhasattwa Nad ,  Srinivas V. Pietambaram ,  Hiroki Tanaka

IPC: H01L23/538 ,  B81B1/00 ,  H01L23/31 ,  H01L23/467 ,  H01L23/498

CPC classification number: H01L23/5386 ,  B81B1/002 ,  H01L23/3121 ,  H01L23/467 ,  H01L23/49866 ,  H01L23/5381 ,  H01L23/5384 ,  B81B2201/0214 ,  H01L24/16 ,  H01L2224/16227

Abstract: Embodiments of a microelectronic assembly includes: an interposer comprising a first portion in contact along an interface with a second portion; a first integrated circuit (IC) die embedded in a dielectric material in the first portion of the interposer; and a second IC die coupled to the first portion of the interposer opposite to the second portion, wherein: the second portion comprises a glass substrate with a channel within the glass substrate, a portion of the channel has an opening at the interface, a conductive pad in the first portion is exposed in the opening, and the conductive pad is coupled to a circuit in at least one of the first IC die or the second IC die.

公开(公告)号：US20240113048A1

公开(公告)日：2024-04-04

申请号：US17957590

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Srinivasan Raman ,  Benjamin Duong ,  Jason Scott Steill ,  Shayan Kaviani ,  Srinivas Venkata Ramanuja Pietambaram ,  Suddhasattwa Nad ,  Brandon C. Marin ,  Gang Duan ,  Yi Yang

IPC: H01L23/64 ,  H01L21/48 ,  H01L23/15 ,  H01L23/498

CPC classification number: H01L23/647 ,  H01L21/486 ,  H01L23/15 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866

Abstract: Various embodiments disclosed relate to embedded components in glass core layers for semiconductor assemblies. The present disclosure includes a semiconductor assembly with a glass core having one or more cavities and a component embedded into the glass core at the one or more cavities portion, the component at least partially embedded in the glass core, and a semiconductor die attached to the substrate.

公开(公告)号：US20240112972A1

公开(公告)日：2024-04-04

申请号：US17958002

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Hiroki Tanaka ,  Robert Alan May ,  Kristof Darmawikarta ,  Bai Nie ,  Brandon C. Marin ,  Jeremy D. Ecton ,  Srinivas Venkata Ramanuja Pietambaram ,  Changhua Liu

IPC: H01L23/15 ,  G02B6/42 ,  G02B6/43

CPC classification number: H01L23/15 ,  G02B6/4204 ,  G02B6/4259 ,  G02B6/426 ,  G02B6/43

Abstract: Disclosed herein are microelectronics package architectures utilizing photo-integrated glass interposers and photonic integrated glass layers and methods of manufacturing the same. The microelectronics packages may include an organic substrate, a photonic integrated glass layer, and a glass interpose. The organic substrate may define through substrate vias. The photonic integrated glass layer may be attached to the organic substrate. The photonic integrated glass layer may include photo detectors. The glass interposer may be attached to the organic substrate. The glass interposer may define through glass vias in optical communication with the photo detectors.

公开(公告)号：US20240105655A1

公开(公告)日：2024-03-28

申请号：US17934721

申请日：2022-09-23

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Kristof Kuwawi Darmawikarta ,  Srinivas V. Pietambaram ,  Gang Duan ,  Suddhasattwa Nad ,  Jeremy Ecton

IPC: H01L23/00 ,  H01L23/13 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L24/13 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5381 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/17 ,  H01L24/73 ,  H01L25/0652 ,  H01L2224/13007 ,  H01L2224/13016 ,  H01L2224/13111 ,  H01L2224/13155 ,  H01L2224/13541 ,  H01L2224/13553 ,  H01L2224/1357 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/3512 ,  H01L2924/381 ,  H01L2924/3841

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a conductive pad having a first surface and an opposing second surface; a conductive via coupled to the first surface of the conductive pad; a microelectronic component having a conductive contact, the conductive contact of the microelectronic component electrically coupled, by an interconnect, to the second surface of the conductive pad, wherein a material of the interconnect includes nickel or tin; and a liner between the interconnect and the second surface of the conductive pad, and wherein a material of the liner includes nickel, palladium, or gold. In some embodiments, a bottom surface of the liner is curved outward towards the conductive pad. In some embodiments, the liner also may be on side surfaces of the interconnect.

公开(公告)号：US20240071933A1

公开(公告)日：2024-02-29

申请号：US17823602

申请日：2022-08-31

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Srinivas V. Pietambaram ,  Gang Duan ,  Suddhasattwa Nad ,  Jeremy Ecton

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L23/5381 ,  H01L23/293 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/5386 ,  H01L24/08 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0652 ,  H01L2224/08145 ,  H01L2224/16148 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/81815 ,  H01L2924/182 ,  H01L2924/186 ,  H01L2924/3512 ,  H01L2924/37001 ,  H01L2924/381 ,  H01L2924/3841

Abstract: Embodiments of a microelectronic assembly comprise: a first layer comprising a plurality of first integrated circuit (IC) dies in an organic dielectric material, the first layer having a first side and a second side opposite to the first side; a second layer on the first side of the first layer, the second layer comprising a second IC die in the organic dielectric material, the second IC die conductively coupling a pair of first IC dies in the plurality of first IC dies of the first layer; and a package substrate coupled to the second side of the first layer. The second IC die is coupled to the pair of first IC dies by interconnects having a pitch less than 60 micrometers between adjacent interconnects, and the pair of first IC dies comprises TSVs conductively coupling circuits in the first IC dies with the interconnects.

公开(公告)号：US20240006289A1

公开(公告)日：2024-01-04

申请号：US17853204

申请日：2022-06-29

Applicant: Intel Corporation

Inventor： Kristof Darmawikarta ,  Kemal Aygun ,  Brandon C. Marin ,  Srinivas Venkata Ramanuja Pietambaram ,  Zhiguo Qian ,  Jiwei Sun

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/66 ,  H01L23/00 ,  H01L23/552 ,  H01L21/768

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L23/49838 ,  H01L23/66 ,  H01L24/16 ,  H01L23/552 ,  H01L21/4853 ,  H01L21/76877 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2924/3025

Abstract: An electronic device includes a substrate including a core layer having a first surface and a second surface opposite the first surface, and at least one coaxial through-hole extending vertically through the core layer from the first surface to the second surface. The coaxial through-hole includes at least a first through-via that includes electrically conductive material extending through the core layer from the first surface to the second surface, and a conductive layer including the same or different electrically conductive material extending vertically through the core layer from the first surface to the second surface and surrounding the first through-via. The conductive layer is to be connected to a ground voltage and is electrically isolated from the first through-via.

公开(公告)号：US20230420378A1

公开(公告)日：2023-12-28

申请号：US17847407

申请日：2022-06-23

Applicant: Intel Corporation

Inventor： Sameer Paital ,  Gang Duan ,  Srinivas V. Pietambaram ,  Kristof Kuwawi Darmawikarta ,  Tchefor Ndukum ,  Vejayakumaran Padavettan ,  Pooja Wadhwa ,  Brandon C. Marin

IPC: H01L23/538 ,  H01L25/065 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/5386 ,  H01L25/0655 ,  H01L23/5383 ,  H01L23/5381 ,  H01L21/4857 ,  H01L24/16 ,  H01L2224/16227

Abstract: Embodiments of a microelectronic assembly comprise an interposer comprising a dielectric material and a pad of conductive material having at least one of a ceramic liner and fin structures; at least two integrated circuit (IC) dies coupled to the interposer; and a bridge die in the interposer conductively coupled to the at least two IC dies. The bridge die has a first face and an opposing second face, the first face of the bridge die is proximate to the at least two IC dies, and the second face of the bridge die is in contact with the pad.

公开(公告)号：US11817349B2

公开(公告)日：2023-11-14

申请号：US16809905

申请日：2020-03-05

Applicant: INTEL CORPORATION

Inventor： Jeremy Ecton ,  Brandon C. Marin ,  Leonel Arana ,  Matthew Tingey ,  Oscar Ojeda ,  Hsin-Wei Wang ,  Suddhasattwa Nad ,  Srinivas Pietambaram ,  Gang Duan

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L21/3213

CPC classification number: H01L21/76885 ,  H01L21/7685 ,  H01L21/76834 ,  H01L21/76852 ,  H01L23/528 ,  H01L23/53238 ,  H01L21/32134

Abstract: A conductive route for an integrated circuit assembly may be formed using a sequence of etching and passivation steps through layers of conductive material, wherein the resulting structure may include a first route portion having a first surface, a second surface, and at least one side surface extending between the first surface and the second surface, an etch stop structure on the first route portion, a second route portion on the etch stop layer, wherein the second route portion has a first surface, a second surface, and at least one side surface extending between the first surface and the second surface, and a passivating layer abutting the at least one side surface of the second route portion.