公开(公告)号：US20160377679A1

公开(公告)日：2016-12-29

申请号：US15039515

申请日：2013-12-26

Applicant: INTEL CORPORATION

Inventor： Daniel S. Froelich ,  Debendra Das Sharma

IPC: G01R31/317 ,  G01R31/3177

Abstract: A test mode signal is generated to include a test pattern and an error reporting sequence. The test mode signal is sent on link that includes one or more extension devices and two or more sublinks. The test mode signal is to be sent on a particular one of the sublinks and is to be used by a receiving device to identify errors on the particular sublink. The error reporting sequence is to be encoded with error information to describe error status of sublinks in the plurality of sublinks.

Abstract translation: 生成测试模式信号以包括测试模式和错误报告序列。 测试模式信号在包括一个或多个扩展设备和两个或更多个子链接的链路上发送。 测试模式信号将被发送在特定的一个子链路上，并且由接收设备使用以识别特定子链路上的错误。 错误报告序列将用错误信息进行编码，以描述多个子链接中的子链接的错误状态。

公开(公告)号：US09355058B2

公开(公告)日：2016-05-31

申请号：US13976937

申请日：2013-03-27

Applicant: Intel Corporation

Inventor： Venkatraman Iyer ,  Darren S. Jue ,  Robert G. Blankenship ,  Fulvio Spagna ,  Debendra Das Sharma ,  Jeffrey C. Swanson

IPC: G06F13/42 ,  G06N99/00

CPC classification number: G06F13/4291 ,  G06F1/24 ,  G06F1/3287 ,  G06F13/1678 ,  G06F13/42 ,  G06F13/4282 ,  G06N99/005

Abstract: A periodic control window is embedded in a link layer data stream to be sent over a serial data link, where the control window is configured to provide physical layer information including information for use in initiating state transitions on the data link. The link layer data can be sent during a link transmitting state of the data link and the control window can interrupt the sending of flits. In one aspect, the information includes link width transition data indicating an attempt to change the number of active lanes on the link.

公开(公告)号：US09262270B2

公开(公告)日：2016-02-16

申请号：US13892894

申请日：2013-05-13

Applicant: Intel Corporation

Inventor： Prahladachar Jayaprakash Bharadwaj ,  Alexander Brown ,  Debendra Das Sharma ,  Junaid Thaliyil

IPC: G06F11/16 ,  G06F11/14 ,  G06F11/07

CPC classification number: G06F11/0745 ,  G06F11/0736 ,  G06F11/0793 ,  G06F11/1415 ,  G06F11/1443

Abstract: A packet is identified at a port of a serial data link, and it is determined that the packet is associated with an error. Entry into an error recovery mode is initiated based on the determination that the packet is associated with the error. Entry into the error recovery mode can cause the serial data link to be forced down. In one aspect, forcing the data link down causes all subsequent inbound packets to be dropped and all pending outbound requests and completions to be aborted during the error recovery mode.

Abstract translation: 在串行数据链路的端口处识别分组，并且确定分组与错误相关联。 基于确定该分组与该错误相关联来进入错误恢复模式。 进入错误恢复模式可能导致串行数据链路被强制关闭。 在一个方面，强制数据链路断开导致所有后续入站分组被丢弃，并且所有待处理的出站请求和完成将在错误恢复模式期间中止。

公开(公告)号：US12135581B2

公开(公告)日：2024-11-05

申请号：US17955234

申请日：2022-09-28

Applicant: Intel Corporation

Inventor： David J. Harriman ,  Debendra Das Sharma ,  Daniel S. Froelich ,  Sean O. Stalley

IPC: G06F1/14 ,  G06F13/42 ,  H04B1/7073 ,  H04L69/14

Abstract: Aspects of the embodiments are directed to systems, methods, and computer program products that facilitate a downstream port to operate in Separate Reference Clocks with Independent Spread Spectrum Clocking (SSC) (SRIS) mode. The system can determine that the downstream port supports one or more SRIS selection mechanisms; determine a system clock configuration from the downstream port to a corresponding upstream port connected to the downstream port by the PCIe-compliant link; set an SRIS mode in the downstream port; and transmit data across the link from the downstream port using the determined system clock configuration.

公开(公告)号：US20240311330A1

公开(公告)日：2024-09-19

申请号：US18399463

申请日：2023-12-28

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Narasimha Lanka ,  Peter Onufryk ,  Swadesh Choudhary ,  Gerald Pasdast ,  Zuoguo Wu ,  Dimitrios Ziakas ,  Sridhar Muthrasanallur

IPC: G06F13/42 ,  G06F13/16

CPC classification number: G06F13/4295 ,  G06F13/1689 ,  G06F2213/0038 ,  G06F2213/0064

Abstract: Embodiments described herein may include apparatus, systems, techniques, or processes that are directed to on-package die-to-die (D2D) interconnects. Specifically, embodiments herein may relate to on-package D2D interconnects for memory that use or relate to the Universal Chiplet Interconnect Express (UCIe) adapter or physical layer (PHY). Other embodiments are described and claimed.

公开(公告)号：US12056029B2

公开(公告)日：2024-08-06

申请号：US17115168

申请日：2020-12-08

Applicant: Intel Corporation

Inventor： Debendra Das Sharma

IPC: G06F11/263 ,  G06F11/10 ,  G06F11/22 ,  G06F11/30 ,  G06F13/40

CPC classification number: G06F11/263 ,  G06F11/1004 ,  G06F11/221 ,  G06F11/2215 ,  G06F11/2247 ,  G06F11/3027 ,  G06F13/4027

Abstract: Systems and devices can include an error injection register comprising error injection parameter information. The systems and devices can also include error injection logic circuit to read error injection parameter information from the error injection register, and inject an error into a flow control unit (Flit); and protocol stack circuitry to transmit the Flit comprising the error on a multilane link. The injected error can be detected by a receiver and used to test and characterize various aspects of a link, such as bit error rate, error correcting code, cyclic redundancy check, replay capabilities, error logging, and other characteristics of the link.

公开(公告)号：US20230325335A1

公开(公告)日：2023-10-12

申请号：US18056774

申请日：2022-11-18

Applicant: Intel Corporation

Inventor： Debendra Das Sharma

IPC: G06F13/40 ,  G06F12/1072 ,  G06F13/42 ,  G06F15/167 ,  G06F13/16

CPC classification number: G06F13/404 ,  G06F12/1072 ,  G06F13/4022 ,  G06F13/4282 ,  G06F15/167 ,  G06F13/1663 ,  G06F2212/1024 ,  G06F2212/1048

Abstract: A shared memory controller receives, from a computing node, a request associated with a memory transaction involving a particular line in a memory pool. The request includes a node address according to an address map of the computing node. An address translation structure is used to translate the first address into a corresponding second address according to a global address map for the memory pool, and the shared memory controller determines that a particular one of a plurality of shared memory controllers is associated with the second address in the global address map and causes the particular shared memory controller to handle the request.

公开(公告)号：US11762802B2

公开(公告)日：2023-09-19

申请号：US16914339

申请日：2020-06-27

Applicant: Intel Corporation

Inventor： Swadesh Choudhary ,  Debendra Das Sharma ,  Lee Albion

IPC: G06F13/42 ,  G06F1/10

CPC classification number: G06F13/42 ,  G06F1/10 ,  G06F13/4221 ,  G06F2213/0026

Abstract: An interface for coupling an agent to a fabric supports a load/store interconnect protocol and includes a header channel implemented on a first subset of a plurality of physical lanes, the first subset of lanes including first lanes to carry a header of a packet based on the interconnect protocol and second lanes to carry metadata for the header. The interface additionally includes a data channel implemented on a separate second subset of the plurality of physical lanes, the second subset of lanes including third lanes to carry a payload of the packet and fourth lanes to carry metadata for the payload.

公开(公告)号：US11743109B2

公开(公告)日：2023-08-29

申请号：US17898825

申请日：2022-08-30

Applicant: Intel Corporation

Inventor： Debendra Das Sharma

IPC: H04L41/0654 ,  H04L41/0816 ,  G06F13/42 ,  H04L41/0604 ,  H04L43/0888 ,  H04L69/22 ,  H04L41/00 ,  H04L67/12 ,  H04L67/02 ,  H04L67/52

CPC classification number: H04L41/0672 ,  G06F13/4226 ,  H04L41/00 ,  H04L41/0627 ,  H04L41/0816 ,  H04L43/0888 ,  H04L69/22 ,  G06F2213/0026 ,  H04L67/02 ,  H04L67/12 ,  H04L67/52

Abstract: In one embodiment, an apparatus includes: a transmitter to send a first plurality of flits to a second device coupled to the apparatus via a link; and a control circuit coupled to the transmitter to change a configuration of the link from a flit-based encoding to a packet-based encoding. In response to the configuration change, the transmitter is to send a first plurality of packets to the second device via the link. Other embodiments are described and claimed.

公开(公告)号：US11741030B2

公开(公告)日：2023-08-29

申请号：US17134242

申请日：2020-12-25

Applicant: Intel Corporation

Inventor： Robert J. Safranek ,  Robert G. Blankenship ,  Venkatraman Iyer ,  Jeff Willey ,  Robert Beers ,  Darren S. Jue ,  Arvind A. Kumar ,  Debendra Das Sharma ,  Jeffrey C. Swanson ,  Bahaa Fahim ,  Vedaraman Geetha ,  Aaron T. Spink ,  Fulvio Spagna ,  Rahul R. Shah ,  Sitaraman V. Iyer ,  William Harry Nale ,  Abhishek Das ,  Simon P. Johnson ,  Yuvraj S. Dhillon ,  Yen-Cheng Liu ,  Raj K. Ramanujan ,  Robert A. Maddox ,  Herbert H. Hum ,  Ashish Gupta

IPC: G06F13/22 ,  H04L49/15 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0831 ,  G06F13/42 ,  G06F8/71 ,  G06F8/77 ,  G06F9/30 ,  G06F12/0806 ,  G06F9/46 ,  G06F13/40 ,  G06F9/445 ,  G06F1/3287 ,  G06F11/10 ,  H04L9/06 ,  G06F12/0808 ,  H04L45/74 ,  G06F8/73 ,  H04L12/46

CPC classification number: G06F13/22 ,  G06F1/3287 ,  G06F8/71 ,  G06F8/77 ,  G06F9/30145 ,  G06F9/44505 ,  G06F9/466 ,  G06F11/1004 ,  G06F12/0806 ,  G06F12/0808 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0833 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4221 ,  G06F13/4282 ,  G06F13/4286 ,  G06F13/4291 ,  H04L9/0662 ,  H04L49/15 ,  G06F8/73 ,  G06F13/4273 ,  G06F2212/1016 ,  G06F2212/2542 ,  G06F2212/622 ,  H04L12/4641 ,  H04L45/74 ,  Y02D10/00 ,  Y02D30/00

Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.