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    Capacitors Including Inner and Outer Electrodes
    42.
    发明申请
    Capacitors Including Inner and Outer Electrodes 有权
    包括内部和外部电极的电容器

    公开(公告)号：US20150187865A1

    公开(公告)日：2015-07-02

    申请号：US14145117

    申请日：2013-12-31

    Applicant: Intermolecular, Inc.

    Inventor： Sergey Barabash ,  Dipankar Pramanik

    IPC: H01L49/02

    CPC classification number: H01L28/75 ,  H01L27/1085 ,  H01L29/66181 ,  H01L29/94

    Abstract: Provided are capacitor stacks for use in integrated circuits and methods of fabricating these stacks. A capacitor stack includes a dielectric layer and one or two inner electrode layers, such as a positive inner electrode layer and a negative inner electrode layer. The inner electrode layers directly interface the dielectric layer. The stack may also include outer electrode layers. The inner electrode layers are either chemically stable or weakly chemically unstable, while in contact with the dielectric layer based on the respective phase diagrams. Furthermore, the electron affinity of the positive inner electrode layer may be less than the electron affinity of the dielectric layer. The sum of the electron affinity and bandgap of the negative inner electrode layer may be less than that of the dielectric layer. In some embodiments, inner electrode layers are formed from heavily doped semiconducting materials, such as gallium arsenide or gallium aluminum arsenide.

    Abstract translation: 提供用于集成电路的电容器堆叠以及制造这些堆叠的方法。 电容器堆叠包括电介质层和一个或两个内部电极层，例如正的内部电极层和负的内部电极层。 内部电极层直接与介电层接触。 堆叠还可以包括外部电极层。 内部电极层是化学稳定的或弱的化学不稳定的，同时基于相应的相图与介电层接触。 此外，正内电极层的电子亲和力可能小于电介质层的电子亲和力。 负的内电极层的电子亲和力和带隙的总和可以小于电介质层的电子亲和力。 在一些实施例中，内部电极层由重掺杂的半导体材料形成，例如砷化镓或砷化镓铝。

    Nonvolatile resistive memory element with an oxygen-gettering layer
    44.
    发明申请
    Nonvolatile resistive memory element with an oxygen-gettering layer 审中-公开
    具有吸氧层的非易失性电阻记忆元件

    公开(公告)号：US20150155485A1

    公开(公告)日：2015-06-04

    申请号：US14618138

    申请日：2015-02-10

    Applicant: Intermolecular Inc.

    Inventor： Tony P. Chiang ,  Dipankar Pramanik ,  Milind Weling

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/1253 ,  G11C13/0002 ,  G11C13/0007 ,  G11C2213/15 ,  G11C2213/33 ,  G11C2213/34 ,  G11C2213/52 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/145 ,  H01L45/146

    Abstract: A nonvolatile resistive memory element includes an oxygen-gettering layer. The oxygen-gettering layer is formed as part of an electrode stack, and is more thermodynamically favorable in gettering oxygen than other layers of the electrode stack. The Gibbs free energy of formation (ΔfG°) of an oxide of the oxygen-gettering layer is less (i.e., more negative) than the Gibbs free energy of formation of an oxide of the adjacent layers of the electrode stack. The oxygen-gettering layer reacts with oxygen present in the adjacent layers of the electrode stack, thereby preventing this oxygen from diffusing into nearby silicon layers to undesirably increase an SiO2 interfacial layer thickness in the memory element and may alternately be selected to decrease such thickness during subsequent processing.

    Abstract translation: 非易失性电阻性存储元件包括吸氧层。 吸氧层形成为电极堆叠的一部分，并且在吸电氧中比电极堆叠的其它层更热力学上更有利。 氧吸收层的氧化物的吉布斯自由能（＆Dgr; fG°）比形成电极堆叠的相邻层的氧化物的吉布斯自由能更少（即更负）。 吸氧层与存在于电极堆叠的相邻层中的氧气反应，从而防止这种氧扩散到附近的硅层中，从而不期望地增加存储元件中的SiO 2界面层厚度，并且可以选择以减少这种厚度 后续处理。

    Barrier design for steering elements
    46.
    发明授权
    Barrier design for steering elements 有权
    导轨元件的屏障设计

    公开(公告)号：US09019744B2

    公开(公告)日：2015-04-28

    申请号：US13728739

    申请日：2012-12-27

    Applicant: Intermolecular, Inc.

    Inventor： Sergey Barabash ,  Mankoo Lee ,  Dipankar Pramanik

    IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24

    CPC classification number: H01L45/147 ,  G11C13/0002 ,  G11C13/003 ,  G11C2213/76 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1266 ,  H01L45/1633

    Abstract: Steering elements suitable for memory device applications can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. In some embodiments, the steering element can include a first electrode, a second electrode, and a graded dielectric layer sandwiched between the two electrodes. The graded dielectric layer can include a varied composition from the first electrode to the second electrode. Graded energy level at the top and/or at the bottom of the band gap, which can be a result of the graded dielectric layer composition, and/or the work function of the electrodes can be configured to suppress tunneling and thermionic current in an off-state of the steering element and/or to maximize a ratio of the tunneling and thermionic currents in an on-state and in an off-state of the steering element.

    Abstract translation: 适用于存储器件应用的转向元件在低电压下可以具有低泄漏电流，以减少非选定器件的潜行电流路径，以及高电压下的高泄漏电流，以最大限度地减少器件切换期间的电压降。 在一些实施例中，操纵元件可以包括第一电极，第二电极和夹在两个电极之间的渐变电介质层。 渐变电介质层可以包括从第一电极到第二电极的不同组成。 带隙的顶部和/或底部的分级能级可以是梯度介电层组成的结果，和/或电极的功函数可以被配置为抑制断开的隧道和热离子电流 和/或最大化导通状态和转向元件断开状态下的隧道和热离子电流的比例。

    Controlling ReRam forming voltage with doping
    47.
    发明授权
    Controlling ReRam forming voltage with doping 有权
    用掺杂控制ReRam形成电压

    公开(公告)号：US09012260B2

    公开(公告)日：2015-04-21

    申请号：US14527276

    申请日：2014-10-29

    Applicant: Intermolecular, Inc.

    Inventor： Sergey Barabash ,  Charlene Chen ,  Dipankar Pramanik

    IPC: H01L29/82 ,  H01L45/00

    CPC classification number: H01L45/1616 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1641

    Abstract: An internal electrical field in a resistive memory element can be formed to reduce the forming voltage. The internal electric field can be formed by incorporating one or more charged layers within the switching dielectric layer of the resistive memory element. The charged layers can include adjacent charge layers to form dipole layers. The charged layers can be formed at or near the interface of the switching dielectric layer with an electrode layer. Further, the charged layer can be oriented with lower valence substitution side towards lower work function electrode, and higher valence substitution side towards higher work function electrode.

    Abstract translation: 可以形成电阻式存储元件中的内部电场以降低成形电压。 可以通过在电阻式存储元件的开关电介质层内并入一个或多个带电层来形成内部电场。 带电层可以包括相邻的电荷层以形成偶极层。 带电层可以在开关电介质层的界面处或附近形成电极层。 此外，带电层可以朝向较低功函电极的较低价取代面取向，而朝较高功函电极取向较高的取代价。

    Amorphous IGZO Devices and Methods for Forming the Same
    48.
    发明申请
    Amorphous IGZO Devices and Methods for Forming the Same 审中-公开
    非晶IGZO器件及其形成方法

    公开(公告)号：US20150079727A1

    公开(公告)日：2015-03-19

    申请号：US14029713

    申请日：2013-09-17

    Applicant: Intermolecular, Inc.

    Inventor： Mankoo Lee ,  Charlene Chen ,  Tony P. Chiang ,  Dipankar Pramanik

    IPC: H01L29/66

    CPC classification number: H01L29/4908 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78693

    Abstract: Embodiments described herein provide improvements to indium-gallium-zinc oxide devices, such as amorphous IGZO thin film transistors, and methods for forming such devices. A relatively thin a-IGZO channel may be utilized. A plasma treatment chemical precursor passivation may be provided to the front-side a-IGZO interface. High-k dielectric materials may be used in the etch-stop layer at the back-side a-IGZO interface. A barrier layer may be formed above the gate electrode before the gate dielectric layer is deposited. The conventional etch-stop layer, typically formed before the source and drain regions are defined, may be replaced by a pre-passivation layer that is formed after the source and drain regions are defined and may include multiple sub-layers.

    Abstract translation: 本文描述的实施例提供了诸如非晶IGZO薄膜晶体管的铟镓镓氧化物器件的改进以及用于形成这种器件的方法。 可以使用相对薄的a-IGZO通道。 可以向前侧a-IGZO界面提供等离子体处理化学前体钝化。 高k电介质材料可用于背面a-IGZO界面的蚀刻停止层。 在栅介质层沉积之前，可以在栅电极上方形成阻挡层。 通常在源极和漏极区域之前形成的常规蚀刻停止层可以由在源极和漏极区域之间形成并且可以包括多个子层形成的预钝化层来代替。

    Memory cell having an integrated two-terminal current limiting resistor
    49.
    发明授权
    Memory cell having an integrated two-terminal current limiting resistor 有权
    具有集成的两端限流电阻的存储单元

    公开(公告)号：US08975727B2

    公开(公告)日：2015-03-10

    申请号：US13721310

    申请日：2012-12-20

    Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

    Inventor： Yun Wang ,  Tony P. Chiang ,  Imran Hashim ,  Tim Minvielle ,  Dipankar Pramanik ,  Takeshi Yamaguchi

    IPC: H01L29/8605 ,  H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/12 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146

    Abstract: A resistor structure incorporated into a resistive switching memory cell with improved performance and lifetime is provided. The resistor structure may be a two-terminal structure designed to reduce the maximum current flowing through a memory cell. A method is also provided for making such a memory cell. The method includes depositing a resistor structure and depositing a variable resistance layer of a resistive switching memory cell of the memory cell, where the resistor structure is disposed in series with the variable resistance layer to limit the switching current of the memory cell. The incorporation of the resistor structure is very useful in obtaining desirable levels of switching currents that meet the switching specification of various types of memory cells. The memory cells may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices.

    Abstract translation: 提供了一种结合到具有改进的性能和寿命的电阻式开关存储单元中的电阻器结构。 电阻器结构可以是设计成减小流过存储器单元的最大电流的两端结构。 还提供了一种用于制造这种存储单元的方法。 该方法包括沉积电阻器结构并沉积存储单元的电阻式开关存储单元的可变电阻层，其中电阻器结构与可变电阻层串联布置以限制存储单元的开关电流。 电阻器结构的结合对于获得满足各种类型的存储器单元的开关规范的期望的开关电流水平是非常有用的。 存储单元可以形成为可用于各种电子设备的大容量非易失性存储器集成电路的一部分。

    Fullerene-based capacitor electrode
    50.
    发明授权
    Fullerene-based capacitor electrode 有权
    富勒烯电容器电极

    公开(公告)号：US08975134B2

    公开(公告)日：2015-03-10

    申请号：US13728026

    申请日：2012-12-27

    Applicant: Intermolecular, Inc.

    Inventor： Sergey Barabash ,  Dipankar Pramanik ,  Xuena Zhang

    IPC: H01L21/8242 ,  H01L21/20 ,  H01L29/40 ,  H01L29/66 ,  B82Y10/00 ,  H01L29/49 ,  H01L29/94

    CPC classification number: H01L29/401 ,  B82Y10/00 ,  H01L21/28255 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66181 ,  H01L29/78 ,  H01L29/94

    Abstract: A doped fullerene-based conductive material can be used as an electrode, which can contact a dielectric such as a high k dielectric. By aligning the dielectric with the band gap of the doped fullerene-based electrode, e.g., the conduction band minimum of the dielectric falls into one of the band gaps of the doped fullerene-based material, thermionic leakage through the dielectric can be reduced, since the excited electrons or holes in the electrode would need higher thermal excitation energy to overcome the band gap before passing through the dielectric layer.

    Abstract translation: 可以使用掺杂的富勒烯类导电材料作为电极，其可以与诸如高k电介质的电介质接触。 通过将电介质与掺杂的富勒烯类电极的带隙对准，例如，电介质的导带最小值落入掺杂的富勒烯类材料的带隙之一中，可以减少通过电介质的热离子泄漏，因为 电极中的激发的电子或空穴将需要更高的热激发能量以克服通过介电层之前的带隙。

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