公开(公告)号：US20150140781A1

公开(公告)日：2015-05-21

申请号：US14605100

申请日：2015-01-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kamal Karda ,  Chandra Mouli

IPC: H01L21/762 ,  H01L27/108

CPC classification number: H01L21/76224 ,  H01L21/76232 ,  H01L27/10823 ,  H01L27/10844 ,  H01L27/10885 ,  H01L27/10891 ,  H01L29/66666

Abstract: A method of formation of an isolation structure for vertical semiconductor devices, the resulting isolation structure, and a memory device to prevent leakage among adjacent vertical semiconductor devices are described.

Abstract translation: 描述了形成用于垂直半导体器件的隔离结构的方法，所得到的隔离结构以及用于防止相邻垂直半导体器件之间泄漏的存储器件。

公开(公告)号：US20150072523A1

公开(公告)日：2015-03-12

申请号：US14543349

申请日：2014-11-17

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu ,  Chandra Mouli

IPC: H01L29/66 ,  H01L21/28

CPC classification number: H01L29/66151 ,  B82Y10/00 ,  H01L21/28 ,  H01L21/283 ,  H01L28/90 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66143 ,  H01L29/872 ,  H01L29/88 ,  H01L45/00

Abstract: Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is deposited along an undulating topography that extends across the pedestal and base, and a second electrode is formed over the least one layer. The first electrode, at least one layer, and second electrode together form a structure that conducts current between the first and second electrodes when voltage of one polarity is applied to the structure, and that inhibits current flow between the first and second electrodes when voltage having a polarity opposite to said one polarity is applied to the structure. Some embodiments include diodes having a first electrode that contains two or more projections extending upwardly from a base, having at least one layer over the first electrode, and having a second electrode over the at least one layer.

Abstract translation: 一些实施例包括形成二极管的方法，其中第一电极形成为具有从基部向上延伸的基座。 沿着延伸穿过基座和基底的波状形貌沉积至少一层，并且在最少一层上形成第二电极。 第一电极，至少一层和第二电极一起形成当一个极性的电压施加到结构时在第一和第二电极之间传导电流的结构，并且当电压具有 与所述一个极性相反的极性被施加到该结构。 一些实施例包括具有第一电极的二极管，该第一电极包含从基底向上延伸的两个或更多个突起，在第一电极上具有至少一个层，并且在该至少一个层上具有第二电极。

公开(公告)号：US20150036405A1

公开(公告)日：2015-02-05

申请号：US14518810

申请日：2014-10-20

Applicant: Micron Technology Inc.

Inventor： Chandra Mouli

IPC: G11C13/00 ,  G11C5/02 ,  G11C11/34

CPC classification number: H01L27/2418 ,  G11C5/02 ,  G11C11/34 ,  G11C11/39 ,  G11C11/4026 ,  G11C11/5664 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0014 ,  G11C13/0016 ,  G11C13/003 ,  G11C2013/009 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76 ,  G11C2216/08 ,  H01L29/6609 ,  H01L45/00 ,  H01L45/141 ,  H01L45/145 ,  H01L45/16

Abstract: Some embodiments include memory devices having a wordline, a bitline, a memory element selectively configurable in one of three or more different resistive states, and a diode configured to allow a current to flow from the wordline through the memory element to the bitline responsive to a voltage being applied across the wordline and the bitline and to decrease the current if the voltage is increased or decreased. Some embodiments include memory devices having a wordline, a bitline, memory element selectively configurable in one of two or more different resistive states, a first diode configured to inhibit a first current from flowing from the bitline to the wordline responsive to a first voltage, and a second diode comprising a dielectric material and configured to allow a second current to flow from the wordline to the bitline responsive to a second voltage.

Abstract translation: 一些实施例包括具有字线，位线，可选择性地以三种或更多种不同电阻状态中的一种状态配置的存储器元件的存储器件，以及被配置为允许电流从字线通过存储器元件流过到位线的二极管， 电压施加在字线和位线之间，并且如果电压增加或减小则降低电流。 一些实施例包括具有字线，位线，可选择性地以两种或多种不同电阻状态之一配置的存储器元件的存储器件，被配置为阻止第一电流响应于第一电压从位线流向字线的第一二极管，以及 第二二极管，包括电介质材料，并被配置为响应于第二电压允许第二电流从字线流到位线。

公开(公告)号：US08766320B2

公开(公告)日：2014-07-01

申请号：US13872762

申请日：2013-04-29

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Jian Li ,  Chandra Mouli

IPC: H01L29/66

CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/1158 ,  H01L27/11582 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/22 ,  H01L29/7926

Abstract: Memory devices are shown that include a body region and a connecting region that is formed from a semiconductor with a lower band gap than the body region. Connecting region configurations can provide increased gate induced drain leakage during an erase operation. Configurations shown can provide a reliable bias to a body region for memory operations such as erasing, and containment of charge in the body region during a boost operation.

Abstract translation: 示出了包括主体区域和由具有比身体区域更低带隙的半导体形成的连接区域的存储器件。 连接区域配置可以在擦除操作期间提供增加的栅极引起的漏极泄漏。 所显示的配置可以提供用于存储器操作的身体区域的可靠偏置，例如在升压操作期间擦除和容纳身体区域中的电荷。

公开(公告)号：US20140146598A1

公开(公告)日：2014-05-29

申请号：US14170019

申请日：2014-01-31

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu ,  Chandra Mouli

IPC: H01L27/108 ,  G11C11/24

CPC classification number: H01L27/108 ,  B82Y10/00 ,  G11C11/24 ,  H01L27/10808 ,  H01L27/10844 ,  H01L27/10873 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/42392 ,  H01L29/78642 ,  H01L51/057

Abstract: Methods and structures are described for reducing leakage currents in semiconductor memory storage cells. Vertically oriented nanorods may be used in the channel region of an access transistor. The nanorod diameter can be made small enough to cause an increase in the electronic band gap energy in the channel region of the access transistor, which may serve to limit channel leakage currents in its off-state. In various embodiments, the access transistor may be electrically coupled to a double-sided capacitor. Memory devices according to embodiments of the invention, and systems including such devices are also disclosed.

Abstract translation: 描述了用于减少半导体存储器存储单元中的漏电流的方法和结构。 垂直取向的纳米棒可用于存取晶体管的沟道区。 纳米棒直径可以做得足够小以引起存取晶体管的沟道区域中的电子带隙能量的增加，这可能有助于将通道漏电流限制在其截止状态。 在各种实施例中，存取晶体管可以电耦合到双面电容器。 还公开了根据本发明的实施例的存储器件，以及包括这种器件的系统。

公开(公告)号：US20130322158A1

公开(公告)日：2013-12-05

申请号：US13959511

申请日：2013-08-05

Applicant: Micron Technology, Inc.

Inventor： Chandra Mouli

IPC: H01L45/00 ,  G11C11/02 ,  G11C13/00

CPC classification number: H01L45/145 ,  G11C11/02 ,  G11C13/0002 ,  G11C13/003 ,  G11C2213/72 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/2418 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/146

Abstract: Some embodiments include memory cells including a memory component having a first conductive material, a second conductive material, and an oxide material between the first conductive material and the second conductive material. A resistance of the memory component is configurable via a current conducted from the first conductive material through the oxide material to the second conductive material. Other embodiments include a diode comprising metal and a dielectric material and a memory component connected in series with the diode. The memory component includes a magnetoresistive material and has a resistance that is changeable via a current conducted through the diode and the magnetoresistive material.

公开(公告)号：US20130224923A1

公开(公告)日：2013-08-29

申请号：US13849962

申请日：2013-03-25

Applicant: Micron Technology, Inc.

Inventor： Chandra Mouli

IPC: H01L29/66

CPC classification number: H01L27/11551 ,  H01L21/02529 ,  H01L21/3148 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/11578 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66795 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/792

Abstract: A stacked non-volatile memory device uses amorphous silicon based thin film transistors stacked vertically. Each layer of transistors or cells is formed from a deposited a-Si channel region layer having a predetermined concentration of carbon to form a carbon rich silicon film or silicon carbide film, depending on the carbon content. The dielectric stack is formed over the channel region layer. In one embodiment, the dielectric stack is an ONO structure. The control gate is formed over the dielectric stack. This structure is repeated vertically to form the stacked structure. In one embodiment, the carbon content of the channel region layer is reduced for each subsequently formed layer.

公开(公告)号：US20010022381A1

公开(公告)日：2001-09-20

申请号：US09144662

申请日：1998-09-01

Applicant: Micron Technology, Inc.

Inventor： Fernando Gonzalez ,  Chandra Mouli

IPC: H01L029/772

CPC classification number: H01L29/4991 ,  H01L21/28512 ,  H01L21/7682 ,  H01L21/76895 ,  H01L23/5226 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/4983 ,  H01L29/66492 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Abstract of DisclosureA semiconductor structure which includes a raised source and a raised drain. The structure also includes a gate located between the source and drains. The gate defines a first gap between the gate and the source and a second gap between the gate and the drain.

Abstract translation: <标题lvl =“0”>摘要公开包括升高源和升高的漏极的半导体结构。 该结构还包括位于源和下水道之间的门。 栅极限定栅极和源极之间的第一间隙以及栅极和漏极之间的第二间隙。

公开(公告)号：US20230402082A1

公开(公告)日：2023-12-14

申请号：US18235955

申请日：2023-08-21

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Chandra Mouli ,  Durai Vishak Nirmal Ramaswamy ,  F. Daniel Gealy

IPC: G11C11/22 ,  H01L29/788 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H10B51/30

CPC classification number: G11C11/223 ,  H01L29/788 ,  H01L29/42392 ,  H01L29/42324 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/78391 ,  H01L29/4234 ,  H01L29/6684 ,  H10B51/30 ,  H01L29/66825 ,  H01L29/7887 ,  H01L29/7889

Abstract: A field effect transistor construction includes a semiconductive channel core. A source/drain region is at opposite ends of the channel core. A gate is proximate a periphery of the channel core. A gate insulator is between the gate and the channel core. The gate insulator has local regions radially there-through that have different capacitance at different circumferential locations relative to the channel core periphery. Additional constructions, and methods, are disclosed.

公开(公告)号：US11769542B2

公开(公告)日：2023-09-26

申请号：US17501464

申请日：2021-10-14

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Chandra Mouli ,  Durai Vishak Nirmal Ramaswamy ,  F. Daniel Gealy

IPC: G11C11/22 ,  H01L29/788 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H10B51/30

CPC classification number: G11C11/223 ,  H01L29/4234 ,  H01L29/42324 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/6684 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7887 ,  H01L29/7889 ,  H01L29/78391 ,  H10B51/30

Abstract: A field effect transistor construction includes a semiconductive channel core. A source/drain region is at opposite ends of the channel core. A gate is proximate a periphery of the channel core. A gate insulator is between the gate and the channel core. The gate insulator has local regions radially there-through that have different capacitance at different circumferential locations relative to the channel core periphery. Additional constructions, and methods, are disclosed.