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    Threshold voltage distribution determination
    41.
    发明授权
    Threshold voltage distribution determination 有权

    公开(公告)号：US09607692B2

    公开(公告)日：2017-03-28

    申请号：US14868604

    申请日：2015-09-29

    Applicant: Micron Technology, Inc.

    Inventor： Qiang Tang ,  Feng Pan ,  Ramin Ghodsi ,  Mark A. Helm

    IPC: G11C11/34 ,  G11C16/06 ,  G11C11/56 ,  G11C7/14 ,  G11C29/02 ,  G11C29/04

    CPC classification number: G11C11/5642 ,  G11C7/14 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0409

    Abstract: Apparatuses and methods for threshold voltage (Vt) distribution determination are described. A number of apparatuses can include sense circuitry configured to determine a first current on a source line of an array of memory cells, the first current corresponding to a first quantity of memory cells of a group of memory cells that conducts in response to a first sensing voltage applied to an access line and determine a second current on the source line, the second current corresponding to a second quantity of memory cells of the group that conducts in response to a second sensing voltage applied to the access line. The number of apparatuses can include a controller configured to determine at least a portion of a Vt distribution corresponding to the group of memory cells based, at least in part, on the first current and the second current.

    Memory cell sensing
    42.
    发明授权
    Memory cell sensing 有权
    记忆单元感应

    公开(公告)号：US09576674B2

    公开(公告)日：2017-02-21

    申请号：US14663179

    申请日：2015-03-19

    Applicant: Micron Technology, Inc.

    Inventor： Matthew Goldman ,  Pranav Kalavade ,  Uday Chandrasekhar ,  Mark A. Helm

    IPC: G11C16/06 ,  G11C16/28 ,  G11C16/26 ,  G11C16/34 ,  G06F12/08 ,  G11C16/04

    CPC classification number: G11C16/28 ,  G06F12/0875 ,  G06F2212/452 ,  G11C16/04 ,  G11C16/26 ,  G11C16/3427

    Abstract: This disclosure concerns memory cell sensing. One or more methods include determining a data state of a first memory cell coupled to a first data line, determining a data state of a third memory cell coupled to a third data line, transferring determined data of at least one of the first and the third memory cells to a data line control unit corresponding to a second data line to which a second memory cell is coupled, the second data line being adjacent to the first data line and the third data line, and determining a data state of the second memory cell based, at least partially, on the transferred determined data.

    Abstract translation: 本公开涉及存储器单元感测。 一种或多种方法包括确定耦合到第一数据线的第一存储器单元的数据状态，确定耦合到第三数据线的第三存储器单元的数据状态，传送第一和第三数据线中的至少一个的确定数据 存储单元连接到与第二存储器单元耦合的第二数据线相对应的数据线控制单元，第二数据线与第一数据线和第三数据线相邻，并且确定第二存储器单元的数据状态 至少部分地基于所转移的确定的数据。

    Data Line Arrangement and Pillar Arrangement in Apparatuses
    45.
    发明申请
    Data Line Arrangement and Pillar Arrangement in Apparatuses 有权
    设备中的数据线布置和柱布置

    公开(公告)号：US20160005761A1

    公开(公告)日：2016-01-07

    申请号：US14850781

    申请日：2015-09-10

    Applicant: Micron Technology, Inc.

    Inventor： Luyen Vu ,  Mark A. Helm

    IPC: H01L27/115 ,  H01L29/04 ,  H01L29/16

    CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/04 ,  H01L29/16

    Abstract: Some embodiments include an apparatus having semiconductor pillars in a substantially hexagonally closest packed arrangement. The hexagonally closest packed arrangement includes a repeating pillar pattern which has at least portions of 7 different pillars. Each of the different pillars in a respective one of the repeating pillar patterns is capable of being electrically coupled to a different data line of a plurality of data lines. Some embodiments include an apparatus having semiconductor pillars in a substantially hexagonally closest packed arrangement. The hexagonally closest packed arrangement includes a repeating pillar pattern having at least portions of 7 different pillars. All 7 different pillars of a repeating pillar pattern are encompassed by a single drain-side select gate (SGD).

    Abstract translation: 一些实施例包括具有基本上六边形最紧密堆积布置的半导体柱的装置。 六边形最紧密的包装布置包括具有7个不同支柱的至少部分的重复支柱图案。 重复柱图案中的相应一个中的每个不同的支柱能够电耦合到多条数据线的不同数据线。 一些实施例包括具有基本上六边形最紧密堆积布置的半导体柱的装置。 六边形最接近的包装布置包括具有7个不同柱的至少一部分的重复柱图形。 重复柱状图案的所有7个不同的柱由单个排水侧选择栅（SGD）包围。

    SENSE OPERATION FLAGS IN A MEMORY DEVICE
    46.
    发明申请
    SENSE OPERATION FLAGS IN A MEMORY DEVICE 有权
    在存储器中识别操作标志

    公开(公告)号：US20150363313A1

    公开(公告)日：2015-12-17

    申请号：US14833175

    申请日：2015-08-24

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Shafqat Ahmed ,  Khaled Hasnat ,  Pranav Kalavade ,  Krishna Parat ,  Aaron Yip ,  Mark A. Helm ,  Andrew Bicksler

    IPC: G06F12/08 ,  G06F13/28 ,  G06F3/06

    CPC classification number: G06F3/0625 ,  G06F3/061 ,  G06F3/0653 ,  G06F3/0665 ,  G06F3/0688 ,  G06F3/0689 ,  G06F12/0804 ,  G06F12/0846 ,  G06F13/28 ,  G06F2212/2022 ,  G06F2212/224 ,  G06F2212/461 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/26 ,  Y02D10/14

    Abstract: Memory devices, methods for programming sense flags, methods for sensing flags, and memory systems are disclosed. In one such memory device, the odd bit lines of a flag memory cell array are connected with a short circuit to a dynamic data cache. The even bit lines of the flag memory cell array are disconnected from the dynamic data cache. When an even page of a main memory cell array is read, the odd flag memory cells, comprising flag data, are read at the same time so that it can be determined whether the odd page of the main memory cell array has been programmed. If the flag data indicates that the odd page has not been programmed, threshold voltage windows can be adjusted to determine the states of the sensed even memory cell page.

    Abstract translation: 公开了存储器件，用于编程感测标志的方法，用于感测标志的方法和存储器系统。 在一个这样的存储器件中，标志存储器单元阵列的奇数位线与短路连接到动态数据高速缓存。 标记存储单元阵列的偶数位线与动态数据高速缓存断开连接。 当读取主存储单元阵列的偶数页时，同时读取包括标志数据的奇数标志存储单元，以便可以确定主存储单元阵列的奇数页是否已被编程。 如果标志数据指示奇数页未被编程，则可以调整阈值电压窗口以确定感测到的偶数存储单元页的状态。

    Methods, devices, and systems for data sensing
    48.
    发明授权
    Methods, devices, and systems for data sensing 有权
    用于数据传感的方法，设备和系统

    公开(公告)号：US09047972B2

    公开(公告)日：2015-06-02

    申请号：US14109375

    申请日：2013-12-17

    Applicant: Micron Technology, Inc.

    Inventor： Mark A. Helm ,  Uday Chandrasekhar

    IPC: G11C29/00 ,  H03M11/00 ,  G11C16/28 ,  G11C16/34 ,  G06F11/10 ,  H03M13/05 ,  H03M13/03

    CPC classification number: G11C16/28 ,  G06F11/10 ,  G06F11/1008 ,  G06F11/1068 ,  G11C16/3454 ,  G11C29/52 ,  H03M13/03 ,  H03M13/05

    Abstract: Methods, devices, and systems for data sensing in a memory system can include performing a number of successive sense operations on a number of memory cells using a number of different sensing voltages, determining a quantity of the number memory cells that change states between consecutive sense operations of the number of successive sense operations, and determining, based at least partially on the determined quantity of the number of memory cells that change states between consecutive sense operations, whether to output hard data corresponding to one of the number of successive sense operations.

    Abstract translation: 存储器系统中用于数据感测的方法，设备和系统可以包括使用多个不同感测电压对多个存储器单元执行多个连续感测操作，确定在连续感测之间改变状态的数量存储器单元的数量 至少部分地确定在连续感测操作之间改变状态的存储器单元的数量的确定量，是否输出对应于多个连续感测操作之一的硬数据的操作。

    MULTI-LAYER CODE RATE ARCHITECTURE FOR COPYBACK BETWEEN PARTITIONS WITH DIFFERENT CODE RATES
    49.
    发明公开
    MULTI-LAYER CODE RATE ARCHITECTURE FOR COPYBACK BETWEEN PARTITIONS WITH DIFFERENT CODE RATES 审中-公开

    公开(公告)号：US20240086282A1

    公开(公告)日：2024-03-14

    申请号：US18511698

    申请日：2023-11-16

    Applicant: Micron Technology, Inc.

    Inventor： Mustafa N. Kaynak ,  Kishore Kumar Muchherla ,  Sivagnanam Parthasarathy ,  James Fitzpatrick ,  Mark A. Helm

    IPC: G06F11/10 ,  H03M13/29

    CPC classification number: G06F11/1068 ,  H03M13/2906

    Abstract: Systems, methods, and apparatus related to a multi-level error correction architecture used for copying data in memory devices. In one approach, user data is stored in the first partition of a non-volatile memory. First error correction code data is generated for the user data and stored with the user data in the first partition. Second error correction code data is generated for the user data and stored outside the first partition. The second error correction code data provides an increased error correcting capability that is compatible with the error correction algorithm used with the first error correction code data. A copyback operation is used to copy the user data and the first error correction code, but not the second error correction code, to a second partition of the non-volatile memory. The second error correction code can be selectively used if there is a need to recover portions of the user data stored in the first partition.

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