公开(公告)号：US20220013434A1

公开(公告)日：2022-01-13

申请号：US17335994

申请日：2021-06-01

Applicant: Micron Technology, Inc.

Inventor： Sameer S. Vadhavkar ,  Xiao Li ,  Steven K. Groothuis ,  Jian Li ,  Jaspreet S. Gandhi ,  James M. Derderian ,  David R. Hembree

IPC: H01L23/44 ,  H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L23/367 ,  H01L25/18 ,  H01L23/04 ,  H01L21/50 ,  H01L25/065 ,  H01L23/373 ,  H01L21/52 ,  H01L21/54 ,  H01L23/053 ,  H01L23/31

Abstract: Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material.

公开(公告)号：US20210305211A1

公开(公告)日：2021-09-30

申请号：US16836283

申请日：2020-03-31

Applicant: Micron Technology, Inc.

Inventor： Travis M. Jensen ,  David R. Hembree

IPC: H01L25/065 ,  H01L25/00

Abstract: Semiconductor devices having redistribution structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor package includes a first semiconductor die including a first redistribution structure and a second semiconductor die including a second redistribution structure. The first and second semiconductor dies can be mounted on a package substrate such that the first and second redistribution structures are aligned with each other. In some embodiments, an interconnect structure can be positioned between the first and second semiconductor dies to electrically couple the first and second redistribution structures to each other. The first and second redistribution structures can be configured such that signal routing between the first and second semiconductor dies can be altered based on the location of the interconnect structure.

公开(公告)号：US10068875B2

公开(公告)日：2018-09-04

申请号：US14920394

申请日：2015-10-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： David R. Hembree

IPC: H01L25/065 ,  H01L23/38 ,  H01L21/56 ,  H01L25/18

Abstract: Apparatuses and methods for heat transfer from packaged semiconductor die are described. For example, an apparatus may include a plurality of die in a stack, and a barrier in close proximity to at least an edge of each of the plurality of die. The apparatus may further include fill material in spaces between adjacent die of the plurality of die and in between the plurality of die and the barrier.

公开(公告)号：US20160372452A1

公开(公告)日：2016-12-22

申请号：US15254586

申请日：2016-09-01

Applicant: Micron Technology, Inc.

Inventor： Sameer S. Vadhavkar ,  Xiao Li ,  Steven K. Groothuis ,  Jian Li ,  Jaspreet S. Gandhi ,  James M. Derderian ,  David R. Hembree

IPC: H01L25/00 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L21/4882 ,  H01L21/50 ,  H01L21/563 ,  H01L23/04 ,  H01L23/36 ,  H01L23/3675 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/167 ,  H01L2224/16145 ,  H01L2225/06568 ,  H01L2225/06589

Abstract: A semiconductor die assembly having high efficiency thermal paths. In one embodiment, the semiconductor die assembly comprises a package support substrate, a first semiconductor die having a peripheral region and a stacking region, and a second semiconductor die attached to the stacking region of the first die such that the peripheral region is lateral of the second die. The assembly further includes a thermal transfer unit having a base attached to the peripheral region of the first die, a cover attached to the base by an adhesive, and a cavity defined by at least cover, wherein the second die is within the cavity. The assembly also includes an underfill in the cavity, wherein a fillet portion of the underfill extends a distance up along a portion of the footing and upward along at least a portion of the base.

公开(公告)号：US09165888B2

公开(公告)日：2015-10-20

申请号：US14222467

申请日：2014-03-21

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Warren M. Farnworth ,  David R. Hembree

IPC: H01L21/50 ,  H01L21/48 ,  H01L21/44 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L23/5384 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/03444 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/05011 ,  H01L2224/05012 ,  H01L2224/05017 ,  H01L2224/05025 ,  H01L2224/05027 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05551 ,  H01L2224/05558 ,  H01L2224/05562 ,  H01L2224/05611 ,  H01L2224/114 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11474 ,  H01L2224/1161 ,  H01L2224/1162 ,  H01L2224/1182 ,  H01L2224/11823 ,  H01L2224/11825 ,  H01L2224/11826 ,  H01L2224/11831 ,  H01L2224/11903 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13075 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13562 ,  H01L2224/13611 ,  H01L2224/13644 ,  H01L2224/13687 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/73257 ,  H01L2224/81139 ,  H01L2224/81191 ,  H01L2224/81205 ,  H01L2224/81345 ,  H01L2224/81365 ,  H01L2224/81815 ,  H01L2224/81898 ,  H01L2224/831 ,  H01L2224/83141 ,  H01L2224/83193 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012

Abstract: Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods are disclosed. A system in accordance with a particular embodiment includes a first semiconductor substrate having a first substrate material, and a penetrating structure carried by the first semiconductor substrate. The system further includes a second semiconductor substrate having a second substrate material with a preformed recess. The penetrating structure of the first semiconductor substrate is received in the recess of the second semiconductor substrate and is mechanically engaged with the recess and secured to the second semiconductor substrate.

Abstract translation: 公开了用于堆叠管芯的互连结构，包括贯穿硅通孔的穿透结构以及相关的系统和方法。 根据特定实施例的系统包括具有第一衬底材料的第一半导体衬底和由第一半导体衬底承载的穿透结构。 该系统还包括第二半导体衬底，该第二半导体衬底具有带有预制凹槽的第二衬底材料。 第一半导体衬底的穿透结构被容纳在第二半导体衬底的凹部中，并且与凹部机械地接合并固定到第二半导体衬底。

公开(公告)号：US08999498B2

公开(公告)日：2015-04-07

申请号：US13751671

申请日：2013-01-28

Applicant: Micron Technology, Inc.

Inventor： David Pratt ,  David R. Hembree

IPC: B32B3/10 ,  B32B3/22 ,  B32B3/30 ,  B32B7/02 ,  B32B7/12 ,  B32B7/14 ,  B32B37/14 ,  H05K13/00 ,  B23B7/02 ,  H01L21/78 ,  B32B37/12

CPC classification number: H01L24/94 ,  B23B7/02 ,  B32B3/30 ,  B32B7/02 ,  B32B7/14 ,  B32B37/1292 ,  B32B37/144 ,  H01L21/78 ,  H01L24/83 ,  H01L2924/14 ,  H05K13/00 ,  Y10T156/19 ,  Y10T156/1994 ,  Y10T428/14 ,  Y10T428/24479 ,  Y10T428/24521 ,  Y10T428/24562 ,  Y10T428/24612 ,  Y10T428/24752 ,  Y10T428/24802 ,  Y10T428/24851 ,  Y10T428/24942 ,  H01L2924/00

Abstract: Methods and apparatuses for releasably attaching support members to microfeature workpieces to support members are disclosed herein. In one embodiment, for example, a method for processing a microfeature workpiece including a plurality of microelectronic dies comprises forming discrete blocks of material at a first side of a support member. The blocks are arranged on the support member in a predetermined pattern. The method also includes depositing an adhesive material into gaps between the individual blocks of material and placing a first side of the workpiece in contact with the adhesive material and/or the blocks. The method further includes cutting through a second side of the workpiece to singulate the dies and to expose at least a portion of the adhesive material in the gaps. The method then includes removing at least approximately all the adhesive material from the support member and/or the workpiece with a solvent.

Abstract translation: 本文公开了用于将支撑构件可释放地附接到微型工件以支撑构件的方法和装置。 在一个实施例中，例如，用于处理包括多个微电子管芯的微特征工件的方法包括在支撑构件的第一侧上形成分立的材料块。 块以预定图案布置在支撑构件上。 该方法还包括将粘合剂材料沉积在单个材料块之间的间隙中，并且使工件的第一侧与粘合剂材料和/或块接触。 该方法还包括切割穿过工件的第二侧以对模具进行切割并且使间隙中的粘合剂材料的至少一部分露出。 该方法然后包括用溶剂从支撑构件和/或工件移除至少几乎所有的粘合剂材料。

公开(公告)号：US20140206145A1

公开(公告)日：2014-07-24

申请号：US14222467

申请日：2014-03-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Owen R. Fay ,  Warren M. Farnworth ,  David R. Hembree

IPC: H01L23/00

CPC classification number: H01L23/5384 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/03444 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/05011 ,  H01L2224/05012 ,  H01L2224/05017 ,  H01L2224/05025 ,  H01L2224/05027 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05551 ,  H01L2224/05558 ,  H01L2224/05562 ,  H01L2224/05611 ,  H01L2224/114 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11474 ,  H01L2224/1161 ,  H01L2224/1162 ,  H01L2224/1182 ,  H01L2224/11823 ,  H01L2224/11825 ,  H01L2224/11826 ,  H01L2224/11831 ,  H01L2224/11903 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13075 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13562 ,  H01L2224/13611 ,  H01L2224/13644 ,  H01L2224/13687 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/73257 ,  H01L2224/81139 ,  H01L2224/81191 ,  H01L2224/81205 ,  H01L2224/81345 ,  H01L2224/81365 ,  H01L2224/81815 ,  H01L2224/81898 ,  H01L2224/831 ,  H01L2224/83141 ,  H01L2224/83193 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012

Abstract: Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods are disclosed. A system in accordance with a particular embodiment includes a first semiconductor substrate having a first substrate material, and a penetrating structure carried by the first semiconductor substrate. The system further includes a second semiconductor substrate having a second substrate material with a preformed recess. The penetrating structure of the first semiconductor substrate is received in the recess of the second semiconductor substrate and is mechanically engaged with the recess and secured to the second semiconductor substrate.

Abstract translation: 公开了用于堆叠管芯的互连结构，包括贯穿硅通孔的穿透结构以及相关的系统和方法。 根据特定实施例的系统包括具有第一衬底材料的第一半导体衬底和由第一半导体衬底承载的穿透结构。 该系统还包括第二半导体衬底，该第二半导体衬底具有带有预制凹槽的第二衬底材料。 第一半导体衬底的穿透结构被容纳在第二半导体衬底的凹部中，并且与凹部机械地接合并固定到第二半导体衬底。