公开(公告)号：US11756894B2

公开(公告)日：2023-09-12

申请号：US16879517

申请日：2020-05-20

Applicant: QUALCOMM Incorporated

Inventor： Jeahyeong Han ,  Rajneesh Kumar ,  Jeongil Jay Kim ,  Chin-Kwan Kim

IPC: H01L23/552 ,  H01L21/48 ,  H01L23/498 ,  H01L23/66 ,  H01L23/00 ,  H01Q1/22 ,  H01Q1/52

CPC classification number: H01L23/552 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/66 ,  H01L24/16 ,  H01Q1/2283 ,  H01Q1/526 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2924/3025

Abstract: Radio-frequency (RF) integrated circuit (IC) (RFIC) packages employing a substrate sidewall partial shield for electro-magnetic interference (EMI) shielding. A RFIC package includes an IC die layer that includes a RFIC die(s) mounted on a substrate that includes substrate metallization layers, a substrate core, and substrate antenna layers. The RFIC package includes an EMI shield surrounding the IC die layer and extending down shared sidewalls of the IC die layer and the substrate. The EMI shield extends down the sidewalls of the IC die layer and substrate metallization layers of the substrate to at least the interface between the substrate metallization layers and the substrate core, and without extending adjacent to the sidewall of the substrate antenna layers. In this manner, antenna performance of the antenna module may not be degraded, because extending the EMI shield down sidewalls of the substrate antenna layers can create a resonance cavity in the substrate.

公开(公告)号：US11637057B2

公开(公告)日：2023-04-25

申请号：US16724247

申请日：2019-12-21

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon Kang ,  Chin-Kwan Kim ,  Aniket Patil ,  Jaehyun Yeon

IPC: H01L23/498 ,  H01L21/48

Abstract: Examples herein provide more integrated circuit packages that allow direct bonding of semiconductor chips to the package, smaller line/spacing of traces, and uniform vias with no capture or cover pads. For example, an integrated circuit (IC) package may include a plurality of pads and a plurality of traces on a substrate with at least two of the plurality of traces located between two of the plurality of pads, and a dielectric layer that completely covers the plurality of traces and partially covers the plurality of pads.

公开(公告)号：US11239573B2

公开(公告)日：2022-02-01

申请号：US16886086

申请日：2020-05-28

Applicant: QUALCOMM Incorporated

Inventor： Milind Shah ,  Chin-Kwan Kim ,  Jaehyun Yeon ,  Rajneesh Kumar ,  Suhyung Hwang

IPC: H01Q23/00 ,  H01Q21/06 ,  H01Q21/30 ,  H01Q1/24 ,  H01Q9/04

Abstract: An antenna-in-package (AiP) module is described. The AiP module includes an antenna sub-module. The antenna sub-module is composed of a first package substrate including an antenna side surface having a first group of antennas placed along a first portion of the antenna side surface and a second group of antennas placed along a second portion of the antenna side surface. The first package substrate is composed of a non-linear portion between the first group of antennas and the second group of antennas. The AiP module includes an active circuit sub-module placed on an active side surface of the first package substrate opposite the first group of antennas or the second group of antennas on the antenna side surface of the first package substrate.

公开(公告)号：US20170271266A1

公开(公告)日：2017-09-21

申请号：US15074750

申请日：2016-03-18

Applicant: QUALCOMM Incorporated

Inventor： Daeik Kim ,  Jie Fu ,  Changhan Yun ,  Chin-Kwan Kim ,  Manuel Aldrete ,  Chengjie Zuo ,  Mario Velez ,  Jonghae Kim

IPC: H01L23/538 ,  H01L21/48

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5383 ,  H01L23/5384 ,  H01L24/19 ,  H01L24/20 ,  H01L24/25 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/2518 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2224/83 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A device and method of fabricating are provided. The device includes a substrate having a first side and an opposite second side, a cavity defined within the substrate from the first side, a die coupled to a floor of the cavity and having a conductive pad on a side of the die distal to the floor of the cavity. A laminate layer coupled to the second side of the substrate may be included. A hole may be drilled, at one time, through layers of the device, through the die, and through the conductive pad. The hole extends through and is defined within the laminate layer (if present), the second side of the substrate, the die, and the conductive pad. A conductive material is provided within the hole and extends between and through the laminate layer (if provided), the second side of the substrate, the die, and the conductive pad.

公开(公告)号：US09768108B2

公开(公告)日：2017-09-19

申请号：US14859318

申请日：2015-09-20

Applicant: QUALCOMM Incorporated

Inventor： Jie Fu ,  Chin-Kwan Kim ,  Manuel Aldrete ,  Milind Pravin Shah ,  Dwayne Richard Shirley

IPC: H01L23/02 ,  H01L23/498 ,  H01L21/48 ,  H01L23/538 ,  H01L25/10

CPC classification number: H01L23/49894 ,  H01L21/4846 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/5389 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/1533

Abstract: An integrated circuit package includes a substrate/interposer assembly having a plurality of conductive contacts and a plurality of conductive posts, such as copper posts, electrically coupled to at least some of the conductive contacts in the substrate/interposer assembly. The conductive posts are surrounded by a protective dielectric, such as a photoimageable dielectric (PID). An integrated circuit die may be disposed on the substrate/interposer assembly within an interior space surrounded by the dielectric. An additional integrated circuit die may be provided in a package-on-package (POP) configuration.

公开(公告)号：US09642259B2

公开(公告)日：2017-05-02

申请号：US14067677

申请日：2013-10-30

Applicant: QUALCOMM Incorporated

Inventor： Chin-Kwan Kim ,  Omar James Bchir ,  Dong Wook Kim ,  Hong Bok We

IPC: H05K7/10 ,  H05K7/12 ,  H05K1/18 ,  H05K1/11 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00

CPC classification number: H05K1/18 ,  H01L23/5383 ,  H01L23/5385 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/15192 ,  H01L2924/15313 ,  H05K1/11 ,  H01L2924/014

Abstract: Some novel features pertain to a substrate that includes a first dielectric layer and a bridge structure. The bridge structure is embedded in the first dielectric layer. The bridge structure is configured to provide an electrical connection between a first die and a second die. The first and second dies are configured to be coupled to the substrate. The bridge structure includes a first set of interconnects and a second dielectric layer. The first set of interconnects is embedded in the first dielectric layer. In some implementations, the bridge structure further includes a second set of interconnects. In some implementations, the second dielectric layer is embedded in the first dielectric layer. The some implementations, the first dielectric layer includes the first set of interconnects of the bridge structure, a second set of interconnects in the bridge structure, and a set of pads in the bridge structure.

公开(公告)号：US20170098633A1

公开(公告)日：2017-04-06

申请号：US15069525

申请日：2016-03-14

Applicant: QUALCOMM Incorporated

Inventor： Rajneesh Kumar ,  Chin-Kwan Kim ,  Brian Roggeman

IPC: H01L25/10 ,  H01L23/538 ,  H01L23/31

CPC classification number: H01L25/105 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/92 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13111 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/01029

Abstract: A package on package (PoP) device that includes a first package, a second package that is coupled to the first package, and at least one gap controller located between the first package and the second package, where the at least one gap controller is configured to provide a minimum gap between the first package and the second package. The first package includes a first electronic package component (e.g., first die). In some implementations, the at least one gap controller is coupled to the first package, but free of coupling with the second package. The at least one gap controller is located on or about a center of the first package. The at least one gap controller may be located between the first electronic package component (e.g., first die) and the second package. The package on package (PoP) device may include an encapsulation layer between the first package and the second package.

公开(公告)号：US20160148864A1

公开(公告)日：2016-05-26

申请号：US14703617

申请日：2015-05-04

Applicant: QUALCOMM Incorporated

Inventor： Jie Fu ,  David Fraser Rae ,  Manuel Aldrete ,  Vladimir Noveski ,  Chin-Kwan Kim

IPC: H01L23/498 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L24/92 ,  H01L23/49811 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/81801 ,  H01L2224/8385 ,  H01L2224/92225 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/152

Abstract: Some features pertain to an integrated circuit device that includes a first package substrate, a first die coupled to the first package substrate, a second package substrate, and a solder joint structure coupled to the first package substrate and the second package substrate. The solder joint structure includes a solder comprising a first melting point temperature, and a conductive material comprising a second melting point temperature that is less than the first melting point temperature. In some implementations, the conductive material is one of at least a homogeneous material and/or a heterogeneous material. In some implementations, the conductive material includes a first electrically conductive material and a second material. The conductive material is an electrically conductive material.

Abstract translation: 一些特征涉及集成电路器件，其包括第一封装衬底，耦合到第一封装衬底的第一管芯，第二封装衬底以及耦合到第一封装衬底和第二封装衬底的焊点结构。 焊接结构包括包含第一熔点温度的焊料和包含小于第一熔点温度的第二熔点温度的导电材料。 在一些实施方案中，导电材料是至少均质材料和/或异质材料之一。 在一些实施方案中，导电材料包括第一导电材料和第二材料。 导电材料是导电材料。

公开(公告)号：US09269681B2

公开(公告)日：2016-02-23

申请号：US13741810

申请日：2013-01-15

Applicant: QUALCOMM Incorporated

Inventor： Houssam W. Jomaa ,  Omar J. Bchir ,  Milind P. Shah ,  Manuel Aldrete ,  Chin-Kwan Kim

IPC: H01L21/56 ,  H01L23/00

CPC classification number: H01L24/11 ,  H01L21/563 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16238 ,  H01L2224/27011 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81444 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2224/16225 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Some implementations provide a semiconductor device that includes a substrate coupled to a die through a thermal compression bonding process. The semiconductor device also includes a trace coupled to the substrate. The trace includes a first conductive material having a first oxidation property. The trace also includes a first surface layer including a second conductive material having a second oxidation property. The second oxidation property is less susceptible to oxidation than the first oxidation property. The first and second conductive materials are configured to provide an electrical path between the die and the substrate. The first surface layer has a thickness that is 0.3 microns (μm) or less.

Abstract translation: 一些实施方案提供了一种半导体器件，其包括通过热压接工艺耦合到管芯的衬底。 半导体器件还包括耦合到衬底的迹线。 痕迹包括具有第一氧化性质的第一导电材料。 迹线还包括第一表面层，其包括具有第二氧化性质的第二导电材料。 第二氧化性比第一氧化性更不易氧化。 第一和第二导电材料被配置为在管芯和衬底之间提供电路径。 第一表面层的厚度为0.3微米（μm）以下。

公开(公告)号：US09269610B2

公开(公告)日：2016-02-23

申请号：US14253798

申请日：2014-04-15

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Chin-Kwan Kim ,  Dong Wook Kim ,  Jae Sik Lee ,  Kyu-Pyung Hwang ,  Young Kyu Song

IPC: H01L21/44 ,  H01L21/768 ,  H01L23/498 ,  H01L21/48 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/768 ,  H01L21/4857 ,  H01L21/76802 ,  H01L21/76838 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/49822 ,  H01L23/5283 ,  H01L23/5329 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/014

Abstract: An integrated circuit (IC) substrate that includes a second patterned metal layer formed in between a first patterned metal layer is disclosed. A dielectric layer formed on the first patterned metal layer separates the two metal layers. A non-conductive layer is formed on the dielectric layer and the second patterned metal layer.

Abstract translation: 公开了一种集成电路（IC）基板，其包括形成在第一图案化金属层之间的第二图案化金属层。 形成在第一图案化金属层上的电介质层分离两个金属层。 在介电层和第二图案化金属层上形成非导电层。