公开(公告)号：US20210351101A1

公开(公告)日：2021-11-11

申请号：US17443307

申请日：2021-07-23

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yusheng LIN ,  Jerome TEYSSEYRE

IPC: H01L23/373 ,  H01L25/07 ,  H01L23/433 ,  H01L21/52 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

Abstract: A method includes disposing a semiconductor die between a first high voltage isolation carrier and a second high voltage isolation carrier, disposing a first molding material in a space between the semiconductor die and the first high voltage isolation carrier, and disposing a conductive spacer between the semiconductor die and the second high voltage isolation carrier. The method further includes encapsulating the first molding material and the conductive spacer with a second molding material.

公开(公告)号：US20210035892A1

公开(公告)日：2021-02-04

申请号：US16733322

申请日：2020-01-03

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Chee Hiong CHEW ,  Atapol PRAJUCKAMOL ,  Stephen ST. GERMAIN ,  Yusheng LIN

IPC: H01L23/495 ,  H01L23/40 ,  H01L23/367 ,  H01L23/00 ,  H01L25/065

Abstract: Implementations of semiconductor packages may include a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the lead frame.

公开(公告)号：US20210028133A1

公开(公告)日：2021-01-28

申请号：US17068172

申请日：2020-10-12

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yusheng LIN ,  Soon Wei WANG ,  Chee Hiong CHEW ,  Francis J. CARNEY

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78

Abstract: A method for fabricating a chip scale package, comprising: providing a wafer; applying a polymer resin on at least part of a first surface of the wafer and to one or more sides of the wafer; and applying a compression mold on at least part of a second surface of the wafer and to one or more sides of the wafer, said first and second surfaces opposing each other.

公开(公告)号：US20210028051A1

公开(公告)日：2021-01-28

申请号：US16661686

申请日：2019-10-23

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Takashi NOMA ,  Noboru OKUBO ,  Yusheng LIN

IPC: H01L21/687 ,  H01L23/00 ,  H01L21/683 ,  H01L21/78 ,  H01L29/861 ,  H01L29/739

Abstract: At least one circuit element may be formed on a front side of a ringed substrate, and the ringed substrate may be mounted on a mounting chuck. The mounting chuck may have an inner raised portion configured to receive the thinned portion of the substrate thereon, and a recessed ring around a perimeter of the mounting chuck configured to receive the outer ring of the ringed substrate therein. At least one solder bump may be formed that is electrically connected to the at least one circuit element, while the ringed wafer is disposed on the mounting chuck.

公开(公告)号：US20200251413A1

公开(公告)日：2020-08-06

申请号：US16853073

申请日：2020-04-20

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yusheng LIN ,  Yenting WEN ,  George CHANG

IPC: H01L23/528 ,  H01L23/492 ,  H01L21/304 ,  H01L21/50 ,  H01L21/78 ,  H01L23/36 ,  H01L23/522 ,  H01L23/532

Abstract: Implementations of semiconductor packages may include: a prefabricated electrically conductive section; two or more metal oxide semiconductor field effect transistors (MOSFET) physically coupled together; and a back metal coupled to the two or more MOSFETs; wherein the electrically conductive section may be coupled to the back metal and may be configured to electrically couple the two or more MOSFETs together during operation of the two or more MOSFETs.

公开(公告)号：US20190267344A1

公开(公告)日：2019-08-29

申请号：US15903677

申请日：2018-02-23

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Michael J. SEDDON ,  Takashi NOMA ,  Kazuo OKADA ,  Hideaki YOSHIMI ,  Naoyuki YOMODA ,  Yusheng LIN

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/78

Abstract: Implementations of semiconductor devices may include a die having a first side and a second side, a contact pad coupled to the first side of the die, and a metal layer coupled to the second side of the die. A thickness of the die may be no more than four times a thickness of the metal layer.

公开(公告)号：US20190229144A1

公开(公告)日：2019-07-25

申请号：US16374720

申请日：2019-04-03

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Larry KINSMAN ,  Yusheng LIN ,  Yu-Te HSIEH ,  Oswald SKEETE ,  Weng-Jin WU ,  Chi-Yao KUO

IPC: H01L27/146 ,  H01L21/56 ,  H01L23/498 ,  H04N5/374 ,  H01L21/48

Abstract: An image sensor semiconductor package (package) includes a printed circuit board (PCB) having a first surface and a second surface opposite the first surface. A complementary metal-oxide semiconductor (CMOS) image sensor (CIS) die has a first surface with a photosensitive region and a second surface opposite the first surface of the CIS die. The second surface of the CIS die is coupled with the first surface of the PCB. A transparent cover is coupled over the photosensitive region of the CIS die. An image signal processor (ISP) is embedded within the PCB. One or more electrical couplers electrically couple the CIS die with the PCB. A plurality of electrical contacts on the second surface of the PCB are electrically coupled with the CIS die and with the ISP. The ISP is located between the plurality of electrical contacts of the second surface of the PCB and the CIS die.

公开(公告)号：US20190181116A1

公开(公告)日：2019-06-13

申请号：US15837857

申请日：2017-12-11

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yusheng LIN

IPC: H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L23/373 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

Abstract: Implementations of semiconductor packages may include: one or more die having a first side and a second side opposite the first side; the first side of the die may include one or more external connection points; a layer of one or more metals comprised on the second side of the one or more die; a second layer of one or more metals comprised on the first layer of one or more metals, wherein the second layer is thicker than the first layer; a molding compound encapsulating five sides of the one or more die and partially encapsulating the second layer of a metal; a plurality of interconnects coupled to the second layer of one or more metals; and two or more bumps coupled to the plurality of interconnects. At least a portion of each of the two or more bumps may be outside a perimeter of the one or more die.

公开(公告)号：US20190116669A1

公开(公告)日：2019-04-18

申请号：US16217753

申请日：2018-12-12

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yushuang YAO ,  Atapol PRAJUCKAMOL ,  Chee Hiong CHEW ,  Francis J. CARNEY ,  Yusheng LIN

IPC: H05K1/18 ,  H05K1/03 ,  H01L23/48 ,  H05K3/34 ,  H05K1/09 ,  H05K1/02 ,  H05K3/40

Abstract: One illustrative method embodiment includes: providing a direct bonded copper (DBC) substrate including a plurality of copper traces; providing a guide plate having protrusions on a surface of the guide plate; mounting hollow bush rings onto the protrusions; mounting the bush rings onto the copper traces by aligning the protrusions of the guide plate with solder units on said copper traces; attaching the bush rings and one or more dies to the copper traces by simultaneously reflowing said solder units and other solder units positioned between the dies and the copper traces; and after said simultaneous reflow, removing the protrusions from the bush rings.

公开(公告)号：US20180211939A1

公开(公告)日：2018-07-26

申请号：US15926127

申请日：2018-03-20

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yusheng LIN ,  Francis J. CARNEY ,  Yenting WEN ,  Chee Hiong CHEW ,  Azhar ARIPIN

IPC: H01L25/07 ,  H01L23/367 ,  H01L21/56 ,  H01L23/00 ,  H01L21/027 ,  H01L21/768 ,  H01L25/00

CPC classification number: H01L25/074 ,  H01L21/0273 ,  H01L21/4853 ,  H01L21/565 ,  H01L21/568 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/16227 ,  H01L2224/24145 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/181 ,  H01L2924/00012

Abstract: Forming a semiconductor package includes coupling electrically conductive elements with a substrate, coupling a first die with one or more of the electrically conductive elements, and at least partially encapsulating the first die and electrically conductive elements in a first mold layer. A first redistribution layer (RDL) is placed over the first mold layer and electrically coupled with the first die. A second die is coupled with the first RDL, and the second die and first RDL are at least partially encapsulated in a second mold layer. A second RDL is formed over the second mold layer and is electrically coupled with the second die. A third mold layer at least partially encapsulates the second RDL. A portion of the substrate is removed to expose (and a solder mask is applied to) surfaces of the electrically conductive elements and of the first mold layer to form a stacked embedded package.