公开(公告)号：US08841773B2

公开(公告)日：2014-09-23

申请号：US13608456

申请日：2012-09-10

Applicant: Hung-Pin Chang ,  Chien-Ming Chiu ,  Tsang-Jiuh Wu ,  Shau-Lin Shue ,  Chen-Hua Yu

Inventor： Hung-Pin Chang ,  Chien-Ming Chiu ,  Tsang-Jiuh Wu ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC: H01L23/48 ,  H01L23/52 ,  H01L21/768 ,  H01L21/683 ,  H01L23/00 ,  H01L23/525

CPC classification number: H01L21/76898 ,  H01L21/6835 ,  H01L23/525 ,  H01L24/13 ,  H01L24/14 ,  H01L2221/68359 ,  H01L2224/13022 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13184 ,  H01L2224/14181 ,  H01L2924/01019 ,  H01L2924/01327 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A multi-layer interconnect structure for stacked die configurations is provided. Through-substrate vias are formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-substrate vias. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-substrate vias. A first conductive element is formed electrically coupled to respective ones of the through-substrate vias and extending over the isolation film. One or more additional layers of isolation films and conductive elements may be formed, with connection elements such as solder balls being electrically coupled to the uppermost conductive elements.

Abstract translation: 提供了用于堆叠管芯配置的多层互连结构。 在半导体衬底中形成贯通衬底通孔。 将半导体衬底的背面变薄以暴露通过衬底的通孔。 在半导体衬底的背面和贯通衬底通孔的暴露部分之后形成隔离膜。 第一导电元件被形成为电耦合到贯穿衬底通孔中的相应通孔并且在隔离膜上延伸。 可以形成一个或多个附加层的隔离膜和导电元件，其中诸如焊球的连接元件电耦合到最上面的导电元件。

公开(公告)号：US08791011B2

公开(公告)日：2014-07-29

申请号：US13775983

申请日：2013-02-25

Applicant: Yung-Chi Lin ,  Weng-Jin Wu ,  Shau-Lin Shue

Inventor： Yung-Chi Lin ,  Weng-Jin Wu ,  Shau-Lin Shue

IPC: H01L21/4763

CPC classification number: H01L21/76871 ,  H01L21/76844 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2924/3011 ,  H01L2924/014 ,  H01L2924/00014

Abstract: In a process, an opening is formed to extend from a front surface of a semiconductor substrate through a part of the semiconductor substrate. A metal seed layer is formed on a sidewall of the opening. A block layer is formed on only a portion of the metal seed layer. A metal layer is formed on the block layer and the metal seed layer to fill the opening.

Abstract translation: 在此过程中，形成从半导体衬底的前表面延伸穿过半导体衬底的一部分的开口。 金属种子层形成在开口的侧壁上。 仅在金属种子层的一部分上形成阻挡层。 在阻挡层和金属种子层上形成金属层以填充开口。

公开(公告)号：US08647925B2

公开(公告)日：2014-02-11

申请号：US12792975

申请日：2010-06-03

Applicant: Wen-Chih Chiou ,  Shau-Lin Shue ,  Weng-Jin Wu ,  Ju-Pin Hung

Inventor： Wen-Chih Chiou ,  Shau-Lin Shue ,  Weng-Jin Wu ,  Ju-Pin Hung

IPC: H01L21/00

CPC classification number: H01L21/76898 ,  H01L21/6836 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/14181 ,  H01L2224/81001 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A wafer is provided with a through via extending a portion of a substrate, an interconnect structure electrically connecting the through via, and a polyimide layer formed on the interconnect structure. Surface modification of the polyimide layer is the formation of a thin dielectric film on the polyimide layer by coating, plasma treatment, chemical treatment, or deposition methods. The thin dielectric film is adhered strongly to the polyimide layer, which can reduce the adhesion between the wafer surface and an adhesive layer formed in subsequent carrier attaching process.

Abstract translation: 晶片设置有延伸基板的一部分的通孔，连接通孔的互连结构和形成在互连结构上的聚酰亚胺层。 聚酰亚胺层的表面改性是通过涂覆，等离子体处理，化学处理或沉积方法在聚酰亚胺层上形成薄的电介质膜。 薄的电介质膜牢固地粘附到聚酰亚胺层，这可以降低晶片表面和随后的载体附接过程中形成的粘合剂层之间的粘合性。

公开(公告)号：US08348719B2

公开(公告)日：2013-01-08

申请号：US11727119

申请日：2007-03-23

Applicant: Hsin-Hsien Lu ,  Liang-Guang Chen ,  Tien-I Bao ,  Shau-Lin Shue

Inventor： Hsin-Hsien Lu ,  Liang-Guang Chen ,  Tien-I Bao ,  Shau-Lin Shue

IPC: B24B49/00 ,  B24B51/00 ,  B24B1/00 ,  B24B7/19 ,  B24B7/30 ,  C25F3/30

CPC classification number: B24B37/22 ,  B24B37/042 ,  B24B37/24

Abstract: Embodiments of a polisher for chemical mechanical planarization. The polisher includes a polishing pad structure containing a first reactant therein, and a second reactant in a polishing environment over the polishing pad structure. The first reactant and the second reactant react endothermically upon contact when polishing a wafer surface between the polishing pad structure and the polishing environment.

Abstract translation: 用于化学机械平面化的抛光机的实施例。 抛光机包括在其中包含第一反应物的抛光垫结构和在抛光环境中的抛光垫结构上的第二反应物。 当抛光抛光垫结构和抛光环境之间的晶片表面时，第一反应物和第二反应物在接触时发生吸热反应。

公开(公告)号：US08236579B2

公开(公告)日：2012-08-07

申请号：US11686142

申请日：2007-03-14

Applicant: Hsiao-Tzu Lu ,  Hung Chang Hsieh ,  Kuei Shun Chen ,  Hsueh-Hung Fu ,  Ching-Hua Hsieh ,  Shau-Lin Shue

Inventor： Hsiao-Tzu Lu ,  Hung Chang Hsieh ,  Kuei Shun Chen ,  Hsueh-Hung Fu ,  Ching-Hua Hsieh ,  Shau-Lin Shue

IPC: H01L21/00

CPC classification number: G03F7/70725 ,  G03F7/70358 ,  G03F7/70783 ,  H01L21/67288

Abstract: Methods and systems for lithographically exposing a substrate based on a curvature profile of the substrate.

Abstract translation: 基于基板的曲率轮廓光刻曝光基板的方法和系统。

公开(公告)号：US08106512B2

公开(公告)日：2012-01-31

申请号：US12845852

申请日：2010-07-29

Applicant: Hsiang-Huan Lee ,  Ming Han Lee ,  Ming-Shih Yeh ,  Chen-Hua Yu ,  Shau-Lin Shue

Inventor： Hsiang-Huan Lee ,  Ming Han Lee ,  Ming-Shih Yeh ,  Chen-Hua Yu ,  Shau-Lin Shue

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/53238 ,  H01L21/28562 ,  H01L21/76846 ,  H01L21/76867 ,  H01L21/76873 ,  H01L21/76883 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The structures and methods described above provide mechanisms to improve interconnect reliability and resistivity. The interconnect reliability and resistivity are improved by using a composite barrier layer, which provides good step coverage, good copper diffusion barrier, and good adhesion with adjacent layers. The composite barrier layer includes an ALD barrier layer to provide good step coverage. The composite barrier layer also includes a barrier-adhesion-enhancing film, which contains at least an element or compound that contains Mn, Cr, V, Ti, or Nb to improve adhesion. The composite barrier layer may also include a Ta or Ti layer between the ALD barrier layer and the barrier-adhesion-enhancing layer.

Abstract translation: 上述结构和方法提供了提高互连可靠性和电阻率的机制。 通过使用复合阻挡层来提高互连的可靠性和电阻率，该复合阻挡层提供良好的台阶覆盖率，良好的铜扩散阻挡层和与相邻层的良好粘附性。 复合阻挡层包括ALD阻挡层以提供良好的阶梯覆盖。 复合阻挡层还包括至少包含含有Mn，Cr，V，Ti或Nb的元素或化合物以提高粘合性的阻隔增粘膜。 复合阻挡层还可以包括在ALD阻挡层和阻挡增粘层之间的Ta或Ti层。

公开(公告)号：US20110259734A1

公开(公告)日：2011-10-27

申请号：US13176839

申请日：2011-07-06

Applicant: Chung-Liang Chang ,  Shau-Lin Shue

Inventor： Chung-Liang Chang ,  Shau-Lin Shue

IPC: C25D7/12 ,  C25D17/06 ,  C25D17/10 ,  C25D17/02

CPC classification number: H01L21/2885 ,  C25D5/18 ,  C25D7/123 ,  C25D17/001 ,  C25D17/007 ,  H01L21/76877

Abstract: An electroplating apparatus for depositing a conductive material on a semiconductor wafer includes a vessel for holding an electroplating bath, a support for holding a semiconductor wafer within the vessel and beneath a surface of the bath; first and second electrodes within the vessel, between which an electrical current may flow causing conductive material to be electrolytically deposited onto the wafer, a third electrode disposed outside of the bath for applying a static electric charge to the wafer, and an electrical power supply coupled with the third electrode.

Abstract translation: 用于在半导体晶片上沉积导电材料的电镀设备包括用于保持电镀槽的容器，用于将半导体晶片保持在容器内并在浴表面下方的支撑体; 容器内的第一和第二电极，电流可以在其间流动，导致导电材料被电解沉积到晶片上;第三电极，设置在电镀槽的外面，用于向晶片施加静电荷;以及电源， 与第三电极。

公开(公告)号：US20110241217A1

公开(公告)日：2011-10-06

申请号：US12750100

申请日：2010-03-30

Applicant: Hung-Pin Chang ,  Chien-Ming Chiu ,  Tsang-Jiuh Wu ,  Shau-Lin Shue ,  Chen-Hua Yu

Inventor： Hung-Pin Chang ,  Chien-Ming Chiu ,  Tsang-Jiuh Wu ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L21/76898 ,  H01L21/6835 ,  H01L23/525 ,  H01L24/13 ,  H01L24/14 ,  H01L2221/68359 ,  H01L2224/13022 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13184 ,  H01L2224/14181 ,  H01L2924/01019 ,  H01L2924/01327 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A multi-layer interconnect structure for stacked die configurations is provided. Through-substrate vias are formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-substrate vias. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-substrate vias. A first conductive element is formed electrically coupled to respective ones of the through-substrate vias and extending over the isolation film. One or more additional layers of isolation films and conductive elements may be formed, with connection elements such as solder balls being electrically coupled to the uppermost conductive elements.

Abstract translation: 提供了用于堆叠管芯配置的多层互连结构。 在半导体衬底中形成贯通衬底通孔。 将半导体衬底的背面变薄以暴露通过衬底的通孔。 在半导体衬底的背面和贯通衬底通孔的暴露部分之后形成隔离膜。 第一导电元件被形成为电耦合到贯穿衬底通孔中的相应通孔并且在隔离膜上延伸。 可以形成一个或多个附加层的隔离膜和导电元件，其中诸如焊球的连接元件电耦合到最上面的导电元件。

公开(公告)号：US07988843B2

公开(公告)日：2011-08-02

申请号：US12705903

申请日：2010-02-15

Applicant: Chung-Liang Chang ,  Shau-Lin Shue

Inventor： Chung-Liang Chang ,  Shau-Lin Shue

IPC: C25D5/34

CPC classification number: H01L21/2885 ,  C25D5/18 ,  C25D7/123 ,  C25D17/001 ,  C25D17/007 ,  H01L21/76877

Abstract: A method of electroplating conductive material on semiconductor wafers controls undesirable surface defects by reducing the electroplating current as the wafer is being initially immersed in a plating bath. Further defect reduction and improved bottom up plating of vias is achieved by applying a static charge on the wafer before it is immersed in the bath, in order to enhance bath accelerators used to control the plating rate. The static charge is applied to the wafer using a supplemental electrode disposed outside the plating bath.

Abstract translation: 在半导体晶片上电镀导电材料的方法通过在晶片最初浸入电镀槽中时减少电镀电流来控制不期望的表面缺陷。 通过在晶片浸入槽中之前对晶片施加静电电荷，以便增强用于控制电镀速率的浴加速器，可实现进一步的缺陷减少和改进的底部电镀通孔。 使用布置在电镀液外部的辅助电极将静电荷施加到晶片。

公开(公告)号：US20110068466A1

公开(公告)日：2011-03-24

申请号：US12832019

申请日：2010-07-07

Applicant: Ming-Fa Chen ,  Wen-Chih Chiou ,  Shau-Lin Shue

Inventor： Ming-Fa Chen ,  Wen-Chih Chiou ,  Shau-Lin Shue

IPC: H01L23/498

CPC classification number: H01L24/81 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/76816 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05025 ,  H01L2224/05546 ,  H01L2224/05547 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/06181 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/14181 ,  H01L2224/811 ,  H01L2224/8136 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2224/05552 ,  H01L2924/00

Abstract: An integrated circuit structure includes a semiconductor substrate having a front surface and a back surface; a conductive via passing through the semiconductor substrate; and a metal feature on the back surface of the semiconductor substrate. The metal feature includes a metal pad overlying and contacting the conductive via, and a metal line over the conductive via. The metal line includes a dual damascene structure. The integrated circuit structure further includes a bump overlying the metal line.

Abstract translation: 集成电路结构包括具有前表面和后表面的半导体衬底; 穿过半导体衬底的导电通孔; 以及在半导体衬底的后表面上的金属特征。 金属特征包括覆盖并接触导电通孔的金属焊盘以及导电通孔上方的金属线。 金属线包括双镶嵌结构。 集成电路结构还包括覆盖金属线的凸块。