公开(公告)号：US10216242B2

公开(公告)日：2019-02-26

申请号：US15610612

申请日：2017-05-31

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Anh Ly ,  Hung Quoc Nguyen

IPC: G11C5/14 ,  G06F1/26 ,  G06F1/28 ,  G11C7/20 ,  G11C16/30 ,  H03K19/0185 ,  G11C11/4074

Abstract: A system and method for improved power sequencing within an embedded flash memory device is disclosed. Various power-on sequences and power-down sequences for a plurality of voltage sources are utilized to improve the performance of an embedded flash memory device. The plurality of voltage sources can be used for different purposes within the embedded flash memory device.

公开(公告)号：US20180268912A1

公开(公告)日：2018-09-20

申请号：US15987735

申请日：2018-05-23

Applicant: Silicon Storage Technology, Inc. ,  The Regents of the University of California

Inventor： Xinjie Guo ,  Farnood Merrikh Bayat ,  Dmitri Strukov ,  Nhan Do ,  Hieu Van Tran ,  Vipin Tiwari

IPC: G11C16/34 ,  H01L27/11558 ,  H01L27/11521 ,  G11C16/26 ,  G11C16/10 ,  G11C16/14

CPC classification number: G11C16/3431 ,  G11C7/18 ,  G11C8/14 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3427 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11558 ,  H01L29/7881

Abstract: A memory device that provides individual memory cell read, write and erase. In an array of memory cells arranged in rows and columns, each column of memory cells includes a column bit line, a first column control gate line for even row cells and a second column control gate line for odd row cells. Each row of memory cells includes a row source line. In another embodiment, each column of memory cells includes a column bit line and a column source line. Each row of memory cells includes a row control gate line. In yet another embodiment, each column of memory cells includes a column bit line and a column erase gate line. Each row of memory cells includes a row source line, a row control gate line, and a row select gate line.

公开(公告)号：US20180145253A1

公开(公告)日：2018-05-24

申请号：US15727776

申请日：2017-10-09

Applicant: Silicon Storage Technology, Inc.

Inventor： Feng Zhou ,  Xian Liu ,  Steven Lemke ,  Santosh Hariharan ,  Hieu Van Tran ,  Nhan Do

IPC: H01L45/00

CPC classification number: H01L45/1608 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1675

Abstract: A method of forming a memory device includes forming a first layer of conductive material having opposing upper and lower surfaces, forming a layer of amorphous silicon on the upper surface of the first layer of conductive material, stripping away the layer of amorphous silicon, wherein some of the amorphous silicon remains in the upper surface of the first layer of conductive material, forming a layer of transition metal oxide material on the upper surface of the first layer of conductive material, and forming a second layer of conductive material on the layer of transition metal oxide material. The method smoothes the upper surface of the bottom electrode, and also provides an bottom electrode upper surface with stable material that is hard to oxidize.

公开(公告)号：US20180144804A1

公开(公告)日：2018-05-24

申请号：US15873872

申请日：2018-01-17

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu

IPC: G11C16/28 ,  G11C16/24 ,  G11C7/06 ,  G11C16/04 ,  G11C16/14

CPC classification number: G11C16/28 ,  G11C7/065 ,  G11C16/0433 ,  G11C16/14 ,  G11C16/24

Abstract: The present invention relates to an improved sensing amplifier and related method for use in read operations in flash memory devices. In one embodiment, a voltage offset is induced in the sensing amplifier through the use of capacitors.

公开(公告)号：US09959927B2

公开(公告)日：2018-05-01

申请号：US15404087

申请日：2017-01-11

Applicant: Silicon Storage Technology, Inc. ,  Agency For Science, Technology And Research

Inventor： Feng Zhou ,  Xian Liu ,  Nhan Do ,  Hieu Van Tran ,  Hung Quoc Nguyen ,  Mark Reiten ,  Zhixian Chen ,  Wang Xinpeng ,  Guo-Qiang Lo

IPC: G11C16/04 ,  G11C13/00 ,  H01L45/00

CPC classification number: G11C13/0007 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16

Abstract: A memory device and method comprising a metal oxide material disposed between and in electrical contact with first and second conductive electrodes, and a voltage source configured to apply a plurality of voltage pulses spaced apart in time across the first and second electrodes. For each one of the voltage pulses, an amplitude of the voltage increases during the voltage pulse.

公开(公告)号：US09910473B2

公开(公告)日：2018-03-06

申请号：US13830246

申请日：2013-03-14

Applicant: Silicon Storage Technology, Inc.

Inventor： Hung Quoc Nguyen ,  Hieu Van Tran ,  Hung Thanh Nguyen

IPC: G06F1/32 ,  G06F1/16 ,  G11C5/14 ,  G11C7/08 ,  G11C7/10 ,  G11C7/20 ,  G11C7/22

CPC classification number: G06F1/32 ,  G11C5/14 ,  G11C7/08 ,  G11C7/1072 ,  G11C7/20 ,  G11C7/222 ,  G11C2207/065 ,  G11C2207/2227

Abstract: An improved method and apparatus for performing power management in a memory device is disclosed.

公开(公告)号：US20180033482A1

公开(公告)日：2018-02-01

申请号：US15597709

申请日：2017-05-17

Applicant: Silicon Storage Technology, Inc. ,  Agency For Science, Technology, and Research

Inventor： Santosh Hariharan ,  Hieu Van Tran ,  Feng Zhou ,  Xian Liu ,  Steven Lemke ,  Nhan Do ,  Zhixian Chen ,  Xinpeng Wang

IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

CPC classification number: G11C13/0011 ,  G11C11/00 ,  G11C13/0007 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0066 ,  G11C2013/0078 ,  G11C2013/0083 ,  G11C2013/0088 ,  G11C2013/0092 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/085 ,  H01L45/146

Abstract: A memory device includes a metal oxide material disposed between and in electrical contact with first and second conductive electrodes, and an electrical current source configured to apply one or more electrical current pulses through the metal oxide material. For each of the one or more electrical current pulses, an amplitude of the electrical current increases over time during the electrical current pulse to form a conductive filament in metal oxide material.

公开(公告)号：US20170337971A1

公开(公告)日：2017-11-23

申请号：US15593231

申请日：2017-05-11

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/14

CPC classification number: G11C16/14 ,  G11C16/0425 ,  G11C16/10

Abstract: A memory device and method of erasing same that includes a substrate of semiconductor material and a plurality of memory cells formed on the substrate and arranged in an array of rows and columns. Each of the memory cells includes spaced apart source and drain regions in the substrate, with a channel region in the substrate extending there between, a floating gate disposed over and insulated from a first portion of the channel region which is adjacent the source region, a select gate disposed over and insulated from a second portion of the channel region which is adjacent the drain region, and a program-erase gate disposed over and insulated from the source region. The program-erase gate lines alone or in combination with the select gate lines, or the source lines, are arranged in the column direction so that each memory cell can be individually programmed, read and erased.

公开(公告)号：US20170179141A1

公开(公告)日：2017-06-22

申请号：US15453829

申请日：2017-03-08

Applicant: Silicon Storage Technology, Inc.

Inventor： Chien-Sheng Su ,  Jeng-Wei Yang ,  Man-Tang Wu ,  Chun-Ming Chen ,  Hieu Van Tran ,  Nhan Do

IPC: H01L27/11521 ,  H01L29/788 ,  H01L29/08 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/1052 ,  H01L27/11551 ,  H01L29/0847 ,  H01L29/42328 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/66825 ,  H01L29/785 ,  H01L29/7856 ,  H01L29/7881

Abstract: A non-volatile memory cell, and method of making, that includes a semiconductor substrate having a fin shaped upper surface with a top surface and two side surfaces. Source and drain regions are formed in the fin shaped upper surface portion with a channel region there between. A conductive floating gate includes a first portion extending along a first portion of the top surface, and second and third portions extending along first portions of the two side surfaces, respectively. A conductive control gate includes a first portion extending along a second portion of the top surface, second and third portions extending along second portions of the two side surfaces respectively, a fourth portion extending up and over at least some of the floating gate first portion, and fifth and sixth portions extending out and over at least some of the floating gate second and third portions respectively.

公开(公告)号：US09678553B2

公开(公告)日：2017-06-13

申请号：US15088038

申请日：2016-03-31

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Anh Ly ,  Hung Quoc Nguyen

IPC: G11C5/14 ,  G06F1/26 ,  G06F1/28 ,  G11C7/20 ,  G11C16/30 ,  H03K19/0185 ,  G11C11/4074

CPC classification number: G06F1/266 ,  G06F1/28 ,  G11C5/14 ,  G11C5/143 ,  G11C5/147 ,  G11C5/148 ,  G11C7/20 ,  G11C11/4074 ,  G11C16/30 ,  H03K19/018521

Abstract: The invention relates to a system and method for improved power sequencing within an embedded flash memory device for a plurality of voltage sources. In one embodiment, a power sequence enabling circuit comprises a PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a first voltage source. During a power up time period, a voltage output from the first voltage source ramps upward, toward a voltage output from a second voltage source through the PMOS transistor. During a power down period, a voltage from the second voltage source ramps downward toward an intermediate voltage greater than zero volts through the first NMOS transistor.