公开(公告)号：US20090001604A1

公开(公告)日：2009-01-01

申请号：US11817669

申请日：2006-03-01

申请人： Daisuke Tanaka ,  Shintaro Yamamichi ,  Hideya Murai ,  Tadanori Shimoto ,  Kaichirou Nakano ,  Katsumi Maeda ,  Katsumi Kikuchi ,  Yoichiro Kurita ,  Kouji Soejima

发明人： Daisuke Tanaka ,  Shintaro Yamamichi ,  Hideya Murai ,  Tadanori Shimoto ,  Kaichirou Nakano ,  Katsumi Maeda ,  Katsumi Kikuchi ,  Yoichiro Kurita ,  Kouji Soejima

IPC分类号： H01L23/485 ,  H01L21/56

CPC分类号： H01L21/563 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/3121 ,  H01L24/16 ,  H01L2221/68345 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/19042 ,  H01L2924/00

摘要： An oxide layer and a metal layer composed of a gold- or platinum-group metal are formed in the stated order on a substrate. A wiring body having a wiring layer, insulating layer, via, and electrode is formed on the metal layer. A semiconductor element is then connected as a flip chip via solder balls on the wiring body electrode, and underfill is introduced between the semiconductor element and the wiring body. Subsequently, a sealing resin layer is formed so as to cover the semiconductor element and the surface of the wiring body on which the semiconductor element is mounted, thus producing a semiconductor package. A high-density, detailed, thin semiconductor package can thereby be realized.

摘要翻译： 在基板上按规定的顺序形成由金或铂族金属构成的氧化物层和金属层。 具有布线层，绝缘层，通孔和电极的布线体形成在金属层上。 然后，半导体元件作为倒装芯片通过布线体电极上的焊球连接，底部填充物被引入到半导体元件与布线体之间。 随后，形成密封树脂层，以覆盖半导体元件和安装有半导体元件的布线体的表面，从而制造半导体封装。 由此可以实现高密度，详细，薄的半导体封装。

公开(公告)号：US20100314778A1

公开(公告)日：2010-12-16

申请号：US12867721

申请日：2009-02-06

申请人： Hideya Murai ,  Kentaro Mori ,  Shintaro Yamamichi ,  Masaya Kawano ,  Kouji Soejima

发明人： Hideya Murai ,  Kentaro Mori ,  Shintaro Yamamichi ,  Masaya Kawano ,  Kouji Soejima

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L24/82 ,  H01L21/4857 ,  H01L21/6835 ,  H01L21/7688 ,  H01L23/5389 ,  H01L24/24 ,  H01L2221/68345 ,  H01L2224/04105 ,  H01L2224/24226 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0106 ,  H01L2924/01078 ,  H01L2924/351 ,  H01L2924/00

摘要： In forming a semiconductor device, an insulation layer is formed on top of a semiconductor chip having a plurality of external terminals. A plurality of interconnections is formed on the insulating layer. External terminals are electrically connected to coordinated interconnections through a plurality of vias formed in the insulation layer. The interconnections are each formed integral with a via conduction part which covers the entire surfaces of the bottom and the sidewall sections of the via. The interconnection is formed so as to be narrower in its region overlying the via than the upper via diameter.

摘要翻译： 在形成半导体器件时，在具有多个外部端子的半导体芯片的顶部上形成绝缘层。 在绝缘层上形成多个互连。 外部端子通过形成在绝缘层中的多个通孔电连接到协调互连。 互连件与通孔导电部分形成一体，通孔导电部分覆盖通孔的底部和侧壁部分的整个表面。 互连形成为在其通孔上方的区域比上通孔直径更窄。

公开(公告)号：US08692364B2

公开(公告)日：2014-04-08

申请号：US13389234

申请日：2010-08-06

申请人： Katsumi Kikuchi ,  Yoshiki Nakashima ,  Kentaro Mori ,  Shintaro Yamamichi

发明人： Katsumi Kikuchi ,  Yoshiki Nakashima ,  Kentaro Mori ,  Shintaro Yamamichi

IPC分类号： H01L23/06 ,  H01L23/48 ,  H01L23/02 ,  H01L23/522 ,  H01L21/4763 ,  H01L21/48

CPC分类号： H05K1/185 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24226 ,  H01L2224/73267 ,  H01L2224/92 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/12044 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19041 ,  H01L2924/3511 ,  H05K1/0366 ,  H05K3/4682 ,  H05K2201/029 ,  H05K2201/10674 ,  H05K2203/063 ,  H05K2203/1469 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

摘要： A semiconductor device includes an embedding layer in which one or more semiconductor element(s) is embedded and one or more interconnect layers as well as one or more insulation layers on one or both sides of the embedding layer. The embedding layer includes a woven cloth formed by reinforcement fibers. The woven cloth has an opening on its site embedding the semiconductor element. The opening is arranged so that direction of the reinforcement fibers will have a preset angle with respect to a direction of a side of or a tangent to at least a portion of the opening, the preset angle being other than a square angle or a zero angle (parallelism).

摘要翻译： 一种半导体器件包括其中嵌入一个或多个半导体元件的嵌入层和一个或多个互连层以及在嵌入层的一侧或两侧上的一个或多个绝缘层。 嵌入层包括由增强纤维形成的织布。 编织布在其内部具有嵌入半导体元件的开口。 开口被布置成使得加强纤维的方向相对于开口的至少一部分的一侧的方向或切线的方向具有预设角度，预设角度不同于方角或零角度 （并行）。

公开(公告)号：US20120133052A1

公开(公告)日：2012-05-31

申请号：US13389234

申请日：2010-08-06

申请人： Katsumi Kikuchi ,  Yoshiki Nakashima ,  Kentaro Mori ,  Shintaro Yamamichi

发明人： Katsumi Kikuchi ,  Yoshiki Nakashima ,  Kentaro Mori ,  Shintaro Yamamichi

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H05K1/185 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24226 ,  H01L2224/73267 ,  H01L2224/92 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/12044 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19041 ,  H01L2924/3511 ,  H05K1/0366 ,  H05K3/4682 ,  H05K2201/029 ,  H05K2201/10674 ,  H05K2203/063 ,  H05K2203/1469 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

摘要： A semiconductor device includes an embedding layer in which one or more semiconductor element(s) is embedded and one or more interconnect layers as well as one or more insulation layers on one or both sides of the embedding layer. The embedding layer includes a woven cloth formed by reinforcement fibers. The woven cloth has an opening on its site embedding the semiconductor element. The opening is arranged so that direction of the reinforcement fibers will have a preset angle with respect to a direction of a side of or a tangent to at least a portion of the opening, the preset angle being other than a square angle or a zero angle (parallelism).

摘要翻译： 一种半导体器件包括其中嵌入一个或多个半导体元件的嵌入层和一个或多个互连层以及在嵌入层的一侧或两侧上的一个或多个绝缘层。 嵌入层包括由增强纤维形成的织布。 编织布在其内部具有嵌入半导体元件的开口。 开口被布置成使得加强纤维的方向相对于开口的至少一部分的一侧的方向或切线的方向具有预设角度，预设角度不同于方角或零角度 （并行）。

公开(公告)号：US08710669B2

公开(公告)日：2014-04-29

申请号：US13320798

申请日：2010-05-18

申请人： Kentaro Mori ,  Yoshiki Nakashima ,  Daisuke Ohshima ,  Katsumi Kikuchi ,  Shintaro Yamamichi

发明人： Kentaro Mori ,  Yoshiki Nakashima ,  Daisuke Ohshima ,  Katsumi Kikuchi ,  Shintaro Yamamichi

IPC分类号： H01L23/498 ,  H01L21/56

CPC分类号： H01L23/5389 ,  H01L23/49827 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/24051 ,  H01L2224/24226 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/3511 ,  H05K1/185 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/10674 ,  H01L2924/00

摘要： A semiconductor device includes a core substrate, and at least one insulating layer and at least one wiring layer that are disposed on a first surface and a second, opposite surface of the substrate. The semiconductor device includes a via disposed in the insulating layer and in the core substrate, and which connects the wiring layers to one another. The semiconductor device includes a semiconductor element mounted on the first surface, forming an electrode terminal that faces up. The semiconductor device includes a connecting portion that penetrates the insulating layer and directly connects the electrode terminal of the semiconductor element and the wiring layer on the first surface. A minimum wiring pitch of this wiring that of any wiring layer on the second surface.

摘要翻译： 半导体器件包括芯基板，以及设置在基板的第一表面和第二相对表面上的至少一个绝缘层和至少一个布线层。 半导体器件包括布置在绝缘层和芯基板中并且将布线层彼此连接的通孔。 半导体器件包括安装在第一表面上的半导体元件，形成面向上的电极端子。 半导体器件包括穿透绝缘层并直接连接半导体元件的电极端子和第一表面上的布线层的连接部分。 该布线的最小布线间距为第二面上任何布线层的布线间距。

公开(公告)号：US20130026653A1

公开(公告)日：2013-01-31

申请号：US13636324

申请日：2011-03-22

申请人： Shintaro Yamamichi ,  Katsumi Kikuchi ,  Yoshiki Nakashima ,  Kentaro Mori

发明人： Shintaro Yamamichi ,  Katsumi Kikuchi ,  Yoshiki Nakashima ,  Kentaro Mori

IPC分类号： H01L21/56 ,  H01L23/48

CPC分类号： H05K1/185 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/66 ,  H01L24/18 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/18 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/82 ,  H01L2224/92244 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K3/4605 ,  H05K2201/09581 ,  H05K2201/10674 ,  H05K2203/1469 ,  H01L2924/00

摘要： In a manufacturing method of a semiconductor device incorporating a semiconductor element in a multilayered wiring structure including a plurality of wiring layers and insulating layers, a semiconductor element is mounted on a silicon support body whose thickness is reduced to a desired thickness and which are equipped with a plurality of through-vias running through in the thickness direction; an insulating layer is formed to embed the semiconductor element; then, a plurality of wiring layers is formed on the opposite surfaces of the silicon support body in connection with the semiconductor element. Thus, it is possible to reduce warping which occurs in proximity to the semiconductor element in manufacturing, thus improving a warping profile in the entirety of a semiconductor device. Additionally, it is possible to prevent semiconductor elements from becoming useless, improve a yield rate, and produce a thin-type semiconductor device with high-density packaging property.

摘要翻译： 在包含多个布线层和绝缘层的多层布线结构中包含半导体元件的半导体器件的制造方法中，将半导体元件安装在硅支撑体上，该硅支撑体的厚度减小到期望的厚度并且配备有 多个穿过厚度方向的通孔; 形成绝缘层以嵌入半导体元件; 那么在与硅半导体元件相连的硅支撑体的相对表面上形成多个布线层。 因此，可以减少在制造中在半导体元件附近发生的翘曲，从而改善整个半导体器件的翘曲轮廓。 此外，可以防止半导体元件变得无用，提高成品率，并且可以生产具有高密度封装性能的薄型半导体器件。

公开(公告)号：US20120068359A1

公开(公告)日：2012-03-22

申请号：US13320798

申请日：2010-05-18

申请人： Kentaro Mori ,  Yoshiki Nakashima ,  Daisuke Ohshima ,  Katsumi Kikuchi ,  Shintaro Yamamichi

发明人： Kentaro Mori ,  Yoshiki Nakashima ,  Daisuke Ohshima ,  Katsumi Kikuchi ,  Shintaro Yamamichi

IPC分类号： H01L23/498 ,  H01L21/56

CPC分类号： H01L23/5389 ,  H01L23/49827 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/24051 ,  H01L2224/24226 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/3511 ,  H05K1/185 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/10674 ,  H01L2924/00

摘要： A semiconductor device comprises: a core substrate; at least one insulating layer and at least one wiring layer which are disposed on each of a first surface of the core substrate and a second surface opposite to the first surface; a via(s) which is disposed in each of the insulating layer and the core substrate, and connects the wiring layers to each other; a semiconductor element, mounted on the first surface of the core substrate, with a surface for forming an electrode terminal(s) facing up; and a connecting portion(s) which penetrates the insulating layer disposed on the first surface and directly connects the electrode terminal of the semiconductor element and the wiring layer disposed on the first surface. A minimum wiring pitch of the wiring layer directly connected to the connecting portion is smaller than that of any of the wiring layer(s) disposed on the second surface.

摘要翻译： 半导体器件包括：芯基板; 至少一个绝缘层和至少一个布线层，其布置在所述芯基板的第一表面和与所述第一表面相对的第二表面中的每一个上; 布置在所述绝缘层和所述芯基板的每一个中的通孔，并且将所述布线层彼此连接; 半导体元件，安装在所述芯基板的第一表面上，具有用于形成面向上的电极端子的表面; 以及穿过设置在第一表面上的绝缘层的直接连接半导体元件的电极端子和布置在第一表面上的布线层的连接部分。 直接连接到连接部分的布线层的最小布线间距小于布置在第二表面上的布线层中的布线层的最小布线间距。

公开(公告)号：US08004074B2

公开(公告)日：2011-08-23

申请号：US12102414

申请日：2008-04-14

申请人： Kentaro Mori ,  Katsumi Kikuchi ,  Shintaro Yamamichi

发明人： Kentaro Mori ,  Katsumi Kikuchi ,  Shintaro Yamamichi

IPC分类号： H01L23/02

CPC分类号： H01L21/6835 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2221/68377 ,  H01L2224/114 ,  H01L2224/116 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81801 ,  H01L2224/85 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device, in which a semiconductor element is mounted on one side of a circuit board that is made up from an insulating layer and a wiring layer, includes metal posts provided on the side of the circuit board on which the semiconductor element is mounted; and a sealing layer provided on the side of the circuit board on which the semiconductor element is mounted such that the semiconductor element is covered and such that only portions of the metal posts are exposed.

摘要翻译： 一种半导体器件，其中半导体元件安装在由绝缘层和布线层构成的电路板的一侧上，包括设置在其上安装有半导体元件的电路板侧的金属柱; 以及密封层，设置在电路板的安装半导体元件的侧面上，使得半导体元件被覆盖，并且仅使金属柱的一部分露出。

公开(公告)号：US20130088841A1

公开(公告)日：2013-04-11

申请号：US13639486

申请日：2011-01-19

申请人： Daisuke Ohshima ,  Kentaro Mori ,  Yoshiki Nakashima ,  Katsumi Kikuchi ,  Shintaro Yamamichi

发明人： Daisuke Ohshima ,  Kentaro Mori ,  Yoshiki Nakashima ,  Katsumi Kikuchi ,  Shintaro Yamamichi

IPC分类号： H05K1/18

CPC分类号： H05K1/183 ,  H01L23/13 ,  H01L23/367 ,  H01L23/49894 ,  H01L23/50 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/221 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/3511 ,  H05K1/0218 ,  H05K1/025 ,  H05K1/185 ,  H05K3/0061 ,  H05K3/4644 ,  H05K2201/09745 ,  H05K2203/1469 ,  H01L2924/00

摘要： The present invention has an object to provide a substrate with a built-in functional element, including the functional element above a metal plate, in which crosstalk noise between signal wirings can be reduced and higher characteristic impedance matching can be achieved. An aspect of the present invention provides a substrate with a built-in functional element, including: a metal plate that includes a concave portion and serves as a ground; the functional element that is placed in the concave portion and includes an electrode terminal; a first insulating layer that covers the functional element and is placed in contact with the metal plate; a first wiring layer including first signal wiring that is opposite the metal plate with the first insulating layer being interposed therebetween; a second insulating layer that covers the first wiring layer; and a ground layer formed of a ground plane that is opposite the first wiring layer with the second insulating layer being interposed therebetween.

摘要翻译： 本发明的目的是提供一种具有内置功能元件的基板，其包括金属板上方的功能元件，其中可以实现信号布线之间的串扰噪声并且可以实现更高的特性阻抗匹配。 本发明的一个方面提供一种具有内置功能元件的基板，包括：金属板，其包括凹部并用作地面; 所述功能元件放置在所述凹部中并且包括电极端子; 覆盖所述功能元件并与所述金属板接触的第一绝缘层; 第一布线层，包括与金属板相对的第一信号布线，其间插入有第一绝缘层; 覆盖所述第一布线层的第二绝缘层; 以及由与第一布线层相对的接地面形成的接地层，其间插入有第二绝缘层。

公开(公告)号：US20130050967A1

公开(公告)日：2013-02-28

申请号：US13634088

申请日：2011-01-19

申请人： Daisuke Ohshima ,  Katsumi Kikuchi ,  Yoshiki Nakashima ,  Kentaro Mori ,  Shintaro Yamamichi

发明人： Daisuke Ohshima ,  Katsumi Kikuchi ,  Yoshiki Nakashima ,  Kentaro Mori ,  Shintaro Yamamichi

IPC分类号： H05K1/18

CPC分类号： H01L23/5389 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/24227 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/18162 ,  H01L2924/3511 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/10416 ,  H01L2924/00

摘要： An object of the present invention is to provide a functional device-embedded substrate that can be thinned and suppress occurrence of warpage. The present invention provides a functional device-embedded substrate including at least a functional device including an electrode terminal, and a covering insulating layer covering at least an electrode terminal surface and a side surface of the functional device, the functional device-embedded substrate including a first pillar structure around the functional device inside the covering insulating layer, the first pillar structure including a material having a thermal expansion coefficient between thermal expansion coefficients of the functional device and the covering insulating layer, wherein the first pillar structure is arranged at a position where a shortest distance from a side surface of the functional device to a side surface of the first pillar structure is smaller than a thickness of the functional device.

摘要翻译： 本发明的目的是提供一种能够变薄并抑制翘曲发生的功能性器件嵌入式基板。 本发明提供一种功能性器件嵌入式基板，其至少包括具有电极端子的功能元件和覆盖所述功能元件的至少电极端子面和侧面的覆盖绝缘层，所述功能元件嵌入型基板包括 第一柱结构包括在功能元件的热膨胀系数与覆盖绝缘层之间具有热膨胀系数的材料的第一柱结构，其中第一柱结构布置在第一柱结构的位置， 从功能元件的侧面到第一柱状结构的侧面的最短距离小于功能元件的厚度。