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公开(公告)号：US08433434B2
公开(公告)日：2013-04-30
申请号：US12766626
申请日：2010-04-23
申请人： Amy Wang , Chen-Hua Yu , Jean Wang , Henry Lo , Francis Ko , Chih-Wei Lai , Kewei Zuo
发明人： Amy Wang , Chen-Hua Yu , Jean Wang , Henry Lo , Francis Ko , Chih-Wei Lai , Kewei Zuo
IPC分类号： G06F19/00
CPC分类号： G05B13/048
摘要： Embodiments of the present invention relate to a method for a near non-adaptive virtual metrology for wafer processing control. In accordance with an embodiment of the present invention, a method for processing control comprises diagnosing a chamber of a processing tool that processes a wafer to identify a key chamber parameter, and controlling the chamber based on the key chamber parameter if the key chamber parameter can be controlled, or compensating a prediction model by changing to a secondary prediction model if the key chamber parameter cannot be sufficiently controlled.
摘要翻译： 本发明的实施例涉及一种用于晶片处理控制的近非自适应虚拟测量方法。 根据本发明的实施例，一种用于处理控制的方法包括：诊断处理工具的室，其处理晶片以识别密钥室参数，以及如果密钥室参数可以基于密钥室参数来控制室 如果密钥室参数不能被充分地控制，则通过改变为次级预测模型来控制或补偿预测模型。
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公开(公告)号：US07879711B2
公开(公告)日：2011-02-01
申请号：US11563973
申请日：2006-11-28
申请人： Chen-Hua Yu , Wen-Chih Chiou , Weng-Jin Wu , Jean Wang
发明人： Chen-Hua Yu , Wen-Chih Chiou , Weng-Jin Wu , Jean Wang
IPC分类号： H01L21/44
CPC分类号： H01L21/76898 , H01L23/3114 , H01L23/3185 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/29 , H01L24/30 , H01L24/32 , H01L24/73 , H01L24/80 , H01L24/81 , H01L24/83 , H01L24/91 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/08145 , H01L2224/13009 , H01L2224/13013 , H01L2224/13014 , H01L2224/13025 , H01L2224/14051 , H01L2224/14135 , H01L2224/14155 , H01L2224/14179 , H01L2224/17517 , H01L2224/29011 , H01L2224/29013 , H01L2224/29035 , H01L2224/29075 , H01L2224/29116 , H01L2224/29124 , H01L2224/29147 , H01L2224/29169 , H01L2224/29184 , H01L2224/29186 , H01L2224/3003 , H01L2224/30155 , H01L2224/73103 , H01L2224/73203 , H01L2224/80895 , H01L2224/80896 , H01L2224/81193 , H01L2224/83193 , H01L2224/9202 , H01L2225/06517 , H01L2225/06541 , H01L2225/06582 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/04941 , H01L2924/04953 , H01L2924/12041 , H01L2924/14 , Y10S438/926 , H01L2924/00 , H01L2924/053 , H01L2924/049 , H01L2924/00014 , H01L2924/00012
摘要： A method includes: forming a transistor gate over a first substrate and at least one first dummy structure within the first substrate; forming an interlayer dielectric (ILD) layer over the gate transistor, the ILD layer including at least one contact structure formed therein and making electrical contact with the transistor gate and at least one first conductive structure formed therethrough at least partially over a surface of the dummy structure; forming a passivation layer over the ILD layer, the passivation layer comprising at least one first pad structure formed therein and making electrical contact with the conductive structure; bonding the first substrate with a second substrate; removing at least a portion of the first dummy structure, thereby forming a first opening; and forming a conductive material within the first opening for formation of a second conductive structure, the second conductive structure being electrically coupled to the first conductive structure.
摘要翻译： 一种方法包括：在第一衬底和第一衬底内的至少一个第一虚拟结构之上形成晶体管栅极; 在所述栅极晶体管上形成层间电介质层（ILD）层，所述ILD层包括形成在其中的至少一个接触结构，并与所述晶体管栅极形成电接触;以及至少一个第一导电结构，其至少部分地形成在所述虚拟 结构体; 在所述ILD层上形成钝化层，所述钝化层包括形成在其中并与所述导电结构电接触的至少一个第一焊盘结构; 用第二衬底接合第一衬底; 去除所述第一虚设结构的至少一部分，从而形成第一开口; 以及在所述第一开口内形成导电材料以形成第二导电结构，所述第二导电结构电耦合到所述第一导电结构。
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公开(公告)号：US20110009998A1
公开(公告)日：2011-01-13
申请号：US12766626
申请日：2010-04-23
申请人： Amy Wang , Chen-Hua Yu , Jean Wang , Henry Lo , Francis Ko , Chih-Wei Lai , Kewei Zuo
发明人： Amy Wang , Chen-Hua Yu , Jean Wang , Henry Lo , Francis Ko , Chih-Wei Lai , Kewei Zuo
IPC分类号： G05B13/04
CPC分类号： G05B13/048
摘要： Embodiments of the present invention relate to a method for a near non-adaptive virtual metrology for wafer processing control. In accordance with an embodiment of the present invention, a method for processing control comprises diagnosing a chamber of a processing tool that processes a wafer to identify a key chamber parameter, and controlling the chamber based on the key chamber parameter if the key chamber parameter can be controlled, or compensating a prediction model by changing to a secondary prediction model if the key chamber parameter cannot be sufficiently controlled.
摘要翻译： 本发明的实施例涉及一种用于晶片处理控制的近非自适应虚拟测量方法。 根据本发明的实施例，一种用于处理控制的方法包括：诊断处理工具的室，其处理晶片以识别密钥室参数，以及如果密钥室参数可以基于密钥室参数来控制室 如果密钥室参数不能被充分地控制，则通过改变为次级预测模型来控制或补偿预测模型。
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公开(公告)号：US20090142903A1
公开(公告)日：2009-06-04
申请号：US12054097
申请日：2008-03-24
申请人： Chen-Hua Yu , Jui-Pin Hung , Weng-Jin Wu , Jean Wang , Wen-Chih Chiou
发明人： Chen-Hua Yu , Jui-Pin Hung , Weng-Jin Wu , Jean Wang , Wen-Chih Chiou
CPC分类号： H01L25/50 , H01L21/67051 , H01L24/28 , H01L24/75 , H01L24/83 , H01L24/94 , H01L2224/8301 , H01L2224/83191 , H01L2224/83192 , H01L2224/8385 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01094 , H01L2924/07802 , H01L2924/14 , H01L2924/1461 , H01L2924/15788 , H01L2924/19042 , Y10T156/14 , H01L2924/00
摘要： The present disclosure provides a bonding apparatus. The bonding apparatus includes a cleaning module designed for cleaning chips; and a chip-to-wafer bonding chamber configured to receive the chips from the cleaning module and designed for bonding the chips to a wafer.
摘要翻译： 本公开提供了一种接合装置。 接合装置包括设计用于清洁芯片的清洁模块; 以及芯片到晶片接合室，其被配置为从所述清洁模块接收所述芯片并被设计用于将所述芯片接合到晶片。
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公开(公告)号：US20080275586A1
公开(公告)日：2008-11-06
申请号：US12025933
申请日：2008-02-05
申请人： Francis Ko , Chih-Wei Lai , Kewei Zuo , Henry Lo , Jean Wang , Ping-Hsu Chen , Chun-Hsien Lin , Chen-Hua Yu
发明人： Francis Ko , Chih-Wei Lai , Kewei Zuo , Henry Lo , Jean Wang , Ping-Hsu Chen , Chun-Hsien Lin , Chen-Hua Yu
IPC分类号： G06F17/00
CPC分类号： G05B23/0221
摘要： A method to enable wafer result prediction includes collecting manufacturing data from various semiconductor manufacturing tools and metrology tools; choosing key parameters using an autokey method based on the manufacturing data; building a virtual metrology based on the key parameters; and predicting wafer results using the virtual metrology.
摘要翻译： 允许晶片结果预测的方法包括从各种半导体制造工具和计量工具收集制造数据; 使用基于制造数据的自动密钥方法选择关键参数; 基于关键参数构建虚拟计量; 并使用虚拟计量来预测晶圆结果。
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公开(公告)号：US08682466B2
公开(公告)日：2014-03-25
申请号：US12025933
申请日：2008-02-05
申请人： Francis Ko , Chih-Wei Lai , Kewei Zuo , Henry Lo , Jean Wang , Ping-Hsu Chen , Chun-Hsien Lim , Chen-Hua Yu
发明人： Francis Ko , Chih-Wei Lai , Kewei Zuo , Henry Lo , Jean Wang , Ping-Hsu Chen , Chun-Hsien Lim , Chen-Hua Yu
IPC分类号： G06F17/50
CPC分类号： G05B23/0221
摘要： A method to enable wafer result prediction includes collecting manufacturing data from various semiconductor manufacturing tools and metrology tools; choosing key parameters using an autokey method based on the manufacturing data; building a virtual metrology based on the key parameters; and predicting wafer results using the virtual metrology.
摘要翻译： 允许晶片结果预测的方法包括从各种半导体制造工具和计量工具收集制造数据; 使用基于制造数据的自动密钥方法选择关键参数; 基于关键参数构建虚拟计量; 并使用虚拟计量来预测晶圆结果。
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公开(公告)号：US07956448B2
公开(公告)日：2011-06-07
申请号：US12878060
申请日：2010-09-09
申请人： Chen-Hua Yu , Wen-Chih Chiou , Weng-Jin Wu , Jean Wang
发明人： Chen-Hua Yu , Wen-Chih Chiou , Weng-Jin Wu , Jean Wang
IPC分类号： H01L23/06
CPC分类号： H01L21/76898 , H01L23/3114 , H01L23/3185 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/29 , H01L24/30 , H01L24/32 , H01L24/73 , H01L24/80 , H01L24/81 , H01L24/83 , H01L24/91 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/08145 , H01L2224/13009 , H01L2224/13013 , H01L2224/13014 , H01L2224/13025 , H01L2224/14051 , H01L2224/14135 , H01L2224/14155 , H01L2224/14179 , H01L2224/17517 , H01L2224/29011 , H01L2224/29013 , H01L2224/29035 , H01L2224/29075 , H01L2224/29116 , H01L2224/29124 , H01L2224/29147 , H01L2224/29169 , H01L2224/29184 , H01L2224/29186 , H01L2224/3003 , H01L2224/30155 , H01L2224/73103 , H01L2224/73203 , H01L2224/80895 , H01L2224/80896 , H01L2224/81193 , H01L2224/83193 , H01L2224/9202 , H01L2225/06517 , H01L2225/06541 , H01L2225/06582 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/04941 , H01L2924/04953 , H01L2924/12041 , H01L2924/14 , Y10S438/926 , H01L2924/00 , H01L2924/053 , H01L2924/049 , H01L2924/00014 , H01L2924/00012
摘要： A stacked structure includes a first substrate bonded to a second substrate such that a first pad structure of the first substrate contacts a second pad structure of the second substrate. A transistor gate is formed over the second substrate, and a first conductive structure extends through the second substrate and has a top surface that is substantially planar with a top surface of the second substrate. An interlayer dielectric (ILD) layer is disposed over the transistor gate, and a passivation layer is disposed over the ILD layer and includes a second pad structure that makes electrical contact with the second conductive structure. The ILD layer includes at least one contact structure that extends through the ILD layer and makes electrical contact with the transistor gate. A second conductive structure is disposed in the ILD layer and is at least partially disposed over a surface of the first conductive structure.
摘要翻译： 层叠结构包括结合到第二基板的第一基板，使得第一基板的第一焊盘结构接触第二基板的第二焊盘结构。 晶体管栅极形成在第二衬底上，并且第一导电结构延伸穿过第二衬底并且具有与第二衬底的顶表面基本平坦的顶表面。 在晶体管栅极上设置层间绝缘层（ILD）层，钝化层设置在ILD层之上，并且包括与第二导电结构电接触的第二焊盘结构。 ILD层包括延伸穿过ILD层并与晶体管栅极电接触的至少一个接触结构。 第二导电结构设置在ILD层中并且至少部分地设置在第一导电结构的表面上。
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公开(公告)号：US20080124845A1
公开(公告)日：2008-05-29
申请号：US11563973
申请日：2006-11-28
申请人： Chen-Hua Yu , Wen-Chih Chiou , Weng-Jin Wu , Jean Wang
发明人： Chen-Hua Yu , Wen-Chih Chiou , Weng-Jin Wu , Jean Wang
IPC分类号： H01L21/335
CPC分类号： H01L21/76898 , H01L23/3114 , H01L23/3185 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/29 , H01L24/30 , H01L24/32 , H01L24/73 , H01L24/80 , H01L24/81 , H01L24/83 , H01L24/91 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/08145 , H01L2224/13009 , H01L2224/13013 , H01L2224/13014 , H01L2224/13025 , H01L2224/14051 , H01L2224/14135 , H01L2224/14155 , H01L2224/14179 , H01L2224/17517 , H01L2224/29011 , H01L2224/29013 , H01L2224/29035 , H01L2224/29075 , H01L2224/29116 , H01L2224/29124 , H01L2224/29147 , H01L2224/29169 , H01L2224/29184 , H01L2224/29186 , H01L2224/3003 , H01L2224/30155 , H01L2224/73103 , H01L2224/73203 , H01L2224/80895 , H01L2224/80896 , H01L2224/81193 , H01L2224/83193 , H01L2224/9202 , H01L2225/06517 , H01L2225/06541 , H01L2225/06582 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/04941 , H01L2924/04953 , H01L2924/12041 , H01L2924/14 , Y10S438/926 , H01L2924/00 , H01L2924/053 , H01L2924/049 , H01L2924/00014 , H01L2924/00012
摘要： A method includes: forming a transistor gate over a first substrate and at least one first dummy structure within the first substrate; forming an interlayer dielectric (ILD) layer over the gate transistor, the ILD layer including at least one contact structure formed therein and making electrical contact with the transistor gate and at least one first conductive structure formed therethrough at least partially over a surface of the dummy structure; forming a passivation layer over the ILD layer, the passivation layer comprising at least one first pad structure formed therein and making electrical contact with the conductive structure; bonding the first substrate with a second substrate; removing at least a portion of the first dummy structure, thereby forming a first opening; and forming a conductive material within the first opening for formation of a second conductive structure, the second conductive structure being electrically coupled to the first conductive structure.
摘要翻译： 一种方法包括：在第一衬底和第一衬底内的至少一个第一虚拟结构之上形成晶体管栅极; 在所述栅极晶体管上形成层间电介质层（ILD）层，所述ILD层包括形成在其中的至少一个接触结构，并与所述晶体管栅极形成电接触;以及至少一个第一导电结构，其至少部分地形成在所述虚拟 结构体; 在所述ILD层上形成钝化层，所述钝化层包括形成在其中并与所述导电结构电接触的至少一个第一焊盘结构; 用第二衬底接合第一衬底; 去除所述第一虚设结构的至少一部分，从而形成第一开口; 以及在所述第一开口内形成导电材料以形成第二导电结构，所述第二导电结构电耦合到所述第一导电结构。
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公开(公告)号：US08387674B2
公开(公告)日：2013-03-05
申请号：US12054097
申请日：2008-03-24
申请人： Chen-Hua Yu , Jui-Pin Hung , Weng-Jin Wu , Jean Wang , Wen-Chih Chiou
发明人： Chen-Hua Yu , Jui-Pin Hung , Weng-Jin Wu , Jean Wang , Wen-Chih Chiou
IPC分类号： B29C65/00
CPC分类号： H01L25/50 , H01L21/67051 , H01L24/28 , H01L24/75 , H01L24/83 , H01L24/94 , H01L2224/8301 , H01L2224/83191 , H01L2224/83192 , H01L2224/8385 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01094 , H01L2924/07802 , H01L2924/14 , H01L2924/1461 , H01L2924/15788 , H01L2924/19042 , Y10T156/14 , H01L2924/00
摘要： The present disclosure provides a bonding apparatus. The bonding apparatus includes a cleaning module designed for cleaning chips; and a chip-to-wafer bonding chamber configured to receive the chips from the cleaning module and designed for bonding the chips to a wafer.
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公开(公告)号：US20100285723A1
公开(公告)日：2010-11-11
申请号：US12437315
申请日：2009-05-07
申请人： Yu-Liang Lin , Chien Ling Hwang , Jean Wang , Chen-Hua Yu
发明人： Yu-Liang Lin , Chien Ling Hwang , Jean Wang , Chen-Hua Yu
CPC分类号： B24B57/02 , B24B37/107 , B24B53/017 , H01L21/02052
摘要： A chemical mechanical polishing (CMP) device for processing a wafer is provided which includes a plate for supporting the wafer to be processed in a face-up orientation, a polishing head opposing the plate, wherein the polishing head includes a rotatable polishing pad operable to contact the wafer while the polishing pad is rotating, and a slurry coating system providing a slurry to the polishing pad for polishing the wafer.
摘要翻译： 提供了一种用于处理晶片的化学机械抛光（CMP）装置，其包括用于以面朝上的方向支撑待加工的晶片的板，与该板相对的抛光头，其中抛光头包括可旋转的抛光垫， 在抛光垫旋转的同时接触晶片;以及浆料涂覆系统，其向抛光垫提供浆料以抛光晶片。
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