公开(公告)号：US09431483B1

公开(公告)日：2016-08-30

申请号：US14658262

申请日：2015-03-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsai-Yu Wen ,  Chin-Sheng Yang ,  Chun-Jen Chen ,  Tsuo-Wen Lu ,  Yu-Ren Wang

IPC: H01L21/02 ,  H01L29/06 ,  H01L21/306 ,  H01L29/161 ,  H01L21/316

CPC classification number: H01L29/0673 ,  H01L21/02164 ,  H01L21/02233 ,  H01L21/02236 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02452 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/02603 ,  H01L21/02612 ,  H01L21/02639 ,  H01L21/02664 ,  H01L21/30604 ,  H01L21/31658 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

Abstract: A method of forming a nanowire includes providing a substrate. The substrate is etched to form at least one fin. Subsequently, a first epitaxial layer is formed on an upper portion of the fin. Later, an undercut is formed on a middle portion the fin. A second epitaxial layer is formed to fill into the undercut. Finally, the fin, the first epitaxial layer and the second epitaxial layer are oxidized to condense the first epitaxial layer and the second epitaxial layer into a germanium-containing nanowire.

Abstract translation: 形成纳米线的方法包括提供基底。 蚀刻衬底以形成至少一个鳍。 随后，在鳍的上部形成第一外延层。 之后，在翅片的中间部分形成底切。 形成第二外延层以填充底切。 最后，将鳍状物，第一外延层和第二外延层氧化以将第一外延层和第二外延层冷凝成含锗纳米线。

公开(公告)号：US20160027950A1

公开(公告)日：2016-01-28

申请号：US14878849

申请日：2015-10-08

Applicant: The Trustees of Dartmouth College

Inventor： Jifeng Liu ,  Haofeng Li ,  Xiaoxin Wang

IPC: H01L31/0687 ,  H01L31/0232 ,  H01L27/144 ,  H01L31/103 ,  H01L31/109 ,  H01L31/18 ,  H01L31/0725

CPC classification number: H01L31/0687 ,  C30B1/023 ,  C30B29/46 ,  G02B6/12004 ,  H01L21/02422 ,  H01L21/0245 ,  H01L21/02452 ,  H01L21/02463 ,  H01L21/02505 ,  H01L21/02543 ,  H01L27/144 ,  H01L27/1446 ,  H01L31/02325 ,  H01L31/0312 ,  H01L31/035281 ,  H01L31/0725 ,  H01L31/103 ,  H01L31/109 ,  H01L31/1812 ,  H01L31/1844 ,  H01L31/1852 ,  H01L31/1864 ,  H01L31/1872 ,  H01L31/204 ,  Y02E10/544 ,  Y02P70/521

Abstract: Methods are discussed for producing single-crystal shapes on amorphous materials. A first method deposits a layer of Germanium-Tin (GeSn) alloy comprising between three and sixteen atomic-percent tin on material incapable of seeding crystal formation, the layer is photolithographically defined into a shape having a point having radius less than 100 nanometers; and the shape is annealed by heating to a temperature below 450 degrees Celsius. A second method also photolithographically defines a shape on a layer of GeSn, then uses a laser to heat and crystalize seed spot on the shape; and anneals the shape by heating and thereby crystalizing additional GeSn alloy of the shape. In embodiments, the crystalized GeSn serves to seed InGaP and/or InGaAs layers that may serve together with the GeSn as layers of a tandem photovoltaic cell.

Abstract translation: 讨论了在无定形材料上制备单晶形状的方法。 第一种方法是在不能接种晶体形成的材料上沉积一层包含三到十六个原子百分比的锡的锗 - 锡（GeSn）合金，该层被光刻地定义为具有半径小于100纳米的点的形状; 并且通过加热至低于450℃的温度来退火形状。 第二种方法还用光刻法定义GeSn层上的形状，然后使用激光来加热晶体结晶晶种; 并通过加热退火形状，从而使另外形状的GeSn合金结晶。 在实施例中，晶体化的GeSn用于使可能与GeSn一起作为串联光伏电池层的InGaP和/或InGaAs层接种。

公开(公告)号：US20150102465A1

公开(公告)日：2015-04-16

申请号：US14512158

申请日：2014-10-10

Applicant: The Board of Trustees of the Leland Stanford Junior University

Inventor： Robert Chen ,  James S. Harris, JR. ,  Suyog Gupta

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/306 ,  H01L29/161 ,  H01L29/16

CPC classification number: H01L21/02535 ,  B81C1/00111 ,  B81C1/00571 ,  B81C2201/014 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02452 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/3065 ,  H01L29/0665 ,  H01L29/0676 ,  H01L29/161 ,  H01S5/1075 ,  H01S5/3427

Abstract: Suspended structures are provided using selective etch technology. Such structures can be protected on all sides when the selective undercut etch is performed, thereby providing excellent control of feature geometry combined with superior material quality.

Abstract translation: 使用选择性蚀刻技术提供悬挂结构。 当执行选择性底切蚀刻时，可以在所有侧面上保护这种结构，从而提供优异的特征几何结合优良的材料质量控制。

公开(公告)号：US08889519B2

公开(公告)日：2014-11-18

申请号：US13812499

申请日：2012-10-12

Applicant: Xiaolong Ma ,  Huaxiang Yin ,  Zuozhen Fu

Inventor： Xiaolong Ma ,  Huaxiang Yin ,  Zuozhen Fu

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L29/161 ,  H01L21/02 ,  H01L21/265 ,  H01L29/10 ,  H01L29/165 ,  H01L21/268 ,  H01L29/51

CPC classification number: H01L29/66477 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02452 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/02675 ,  H01L21/26506 ,  H01L21/268 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66575 ,  H01L29/66651 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7848

Abstract: The present invention discloses a semiconductor device, comprising: a substrate, a gate stack structure on the substrate, source and drain regions in the substrate on both sides of the gate stack structure, and a channel region between the source and drain regions in the substrate, characterized in that at least one of the source and drain regions comprises a GeSn alloy. In accordance with the semiconductor device and method for manufacturing the same of the present invention, GeSn stressed source and drain regions with high concentration of Sn is formed by implanting precursors and performing a laser rapid annealing, thus the device carrier mobility of the channel region is effectively enhanced and the device drive capability is further improved.

Abstract translation: 本发明公开了一种半导体器件，包括：衬底，衬底上的栅极堆叠结构，栅极堆叠结构两侧的衬底中的源极和漏极区域以及衬底中的源极和漏极区域之间的沟道区域 其特征在于源区和漏区中的至少一个包括GeSn合金。 根据本发明的半导体器件及其制造方法，通过注入前体并进行激光快速退火形成GeSn应力的高浓度Sn的源区和漏极区，因此沟道区的器件载流子迁移率为 有效提高了设备​​驱动能力。

公开(公告)号：US20140053894A1

公开(公告)日：2014-02-27

申请号：US13593305

申请日：2012-08-23

Applicant: Radek Roucka ,  Michael Lebby ,  Scott Semans

Inventor： Radek Roucka ,  Michael Lebby ,  Scott Semans

IPC: H01L31/0336 ,  H01L31/18 ,  H01L29/267 ,  H01L21/20

CPC classification number: H01L29/267 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02452 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/02543 ,  H01L21/02546 ,  H01L31/0687 ,  H01L31/0693 ,  H01L31/1852 ,  Y02E10/544

Abstract: A method of fabricating a solar cell on a silicon substrate includes providing a crystalline silicon substrate, selecting a grading profile, epitaxially growing a template on the silicon substrate including a single crystal GeSn layer using the grading profile to grade Sn through the layer. The single crystal GeSn layer has a thickness in a range of approximately 3 μm to approximately 5 μm. At least two layers of high band gap material are epitaxially and sequentially grown on the template to form at least three junctions. The grading profile starts with the Sn at or near zero with the Ge at zero, the percentage of Sn varies to a maximum mid-area, and reduces the percentage of Sn to zero adjacent an upper surface.

Abstract translation: 在硅衬底上制造太阳能电池的方法包括：提供晶体硅衬底，选择分级分布，使用分级分布在包括单晶GeSn层的硅衬底上外延生长模板，以通过该层对Sn进行分级。 单晶GeSn层的厚度在约3μm至约5μm的范围内。 外延至少两层高带隙材料，并在模板上顺序生长以形成至少三个结。 分级轮廓从Sn处于零附近开始，其中Ge处于零处，Sn的百分比变化到最大中间区域，并且将Sn的百分比减小到与上表面相邻的零。

公开(公告)号：US08647439B2

公开(公告)日：2014-02-11

申请号：US13456500

申请日：2012-04-26

Applicant: Errol Antonio C. Sanchez ,  Yi-Chiau Huang

Inventor： Errol Antonio C. Sanchez ,  Yi-Chiau Huang

IPC: H01L21/3065 ,  H01L21/306

CPC classification number: H01L21/02661 ,  H01L21/0245 ,  H01L21/02452 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/3065

Abstract: Methods of preparing a clean surface of germanium tin or silicon germanium tin layers for subsequent deposition are provided. An overlayer of Ge, doped Ge, another GeSn or SiGeSn layer, a doped GeSn or SiGeSn layer, an insulator, or a metal can be deposited on a prepared GeSn or SiGeSn layer by positioning a substrate with an exposed germanium tin or silicon germanium tin layer in a processing chamber, heating the processing chamber and flowing a halide gas into the processing chamber to etch the surface of the substrate using either thermal or plasma assisted etching followed by depositing an overlayer on the substantially oxide free and contaminant free surface. Methods can also include the placement and etching of a sacrificial layer, a thermal clean using rapid thermal annealing, or a process in a plasma of nitrogen trifluoride and ammonia gas.

Abstract translation: 提供了制备用于后续沉积的锗锡或硅锗锡层的洁净表面的方法。 通过用暴露的锗锡或硅锗锡定位衬底，可以在制备的GeSn或SiGeSn层上沉积Ge，掺杂Ge，另一GeSn或SiGeSn层，掺杂GeSn或SiGeSn层，绝缘体或金属的覆盖层 层，加热处理室并使卤化物气体流入处理室，以使用热或等离子体辅助蚀刻来蚀刻衬底的表面，随后在基本上无氧化物和无污染物的表面上沉积覆盖层。 方法还可以包括牺牲层的放置和蚀刻，使用快速热退火的热清洁，或三氟化氮和氨气的等离子体中的工艺。

公开(公告)号：US20130288480A1

公开(公告)日：2013-10-31

申请号：US13456500

申请日：2012-04-26

Applicant: ERROL ANTONIO C. SANCHEZ ,  YI-CHIAU HUANG

Inventor： ERROL ANTONIO C. SANCHEZ ,  YI-CHIAU HUANG

IPC: H01L21/3065 ,  H01L21/306

CPC classification number: H01L21/02661 ,  H01L21/0245 ,  H01L21/02452 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/3065

Abstract: Methods of preparing a clean surface of germanium tin or silicon germanium tin layers for subsequent deposition are provided. An overlayer of Ge, doped Ge, another GeSn or SiGeSn layer, a doped GeSn or SiGeSn layer, an insulator, or a metal can be deposited on a prepared GeSn or SiGeSn layer by positioning a substrate with an exposed germanium tin or silicon germanium tin layer in a processing chamber, heating the processing chamber and flowing a halide gas into the processing chamber to etch the surface of the substrate using either thermal or plasma assisted etching followed by depositing an overlayer on the substantially oxide free and contaminant free surface. Methods can also include the placement and etching of a sacrificial layer, a thermal clean using rapid thermal annealing, or a process in a plasma of nitrogen trifluoride and ammonia gas.

Abstract translation: 提供了制备用于后续沉积的锗锡或硅锗锡层的洁净表面的方法。 通过用暴露的锗锡或硅锗锡定位衬底，可以在制备的GeSn或SiGeSn层上沉积Ge，掺杂Ge，另一GeSn或SiGeSn层，掺杂GeSn或SiGeSn层，绝缘体或金属的覆盖层 层，加热处理室并使卤化物气体流入处理室，以使用热或等离子体辅助蚀刻来蚀刻衬底的表面，随后在基本上无氧化物和无污染物的表面上沉积覆盖层。 方法还可以包括牺牲层的放置和蚀刻，使用快速热退火的热清洁，或三氟化氮和氨气的等离子体中的工艺。

公开(公告)号：US20110316051A1

公开(公告)日：2011-12-29

申请号：US13255648

申请日：2010-03-08

Applicant: Tomoyuki Takada ,  Masahiko Hata ,  Sadanori Yamanaka

Inventor： Tomoyuki Takada ,  Masahiko Hata ,  Sadanori Yamanaka

IPC: H01L29/165 ,  H01L21/20

CPC classification number: H01L21/0237 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02452 ,  H01L21/02463 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/02642 ,  H01L29/107 ,  H01L29/73 ,  H01L29/7371 ,  H01L29/772

Abstract: The semiconductor wafer includes: a base wafer; and an inhibition layer that is disposed on the base wafer as one piece or to be separate portions from each other, and inhibits growth of a crystal of a compound semiconductor, where the inhibition layer has a plurality of first opening regions that have a plurality of openings penetrating the inhibition layer and leading to the base wafer, each of the plurality of first opening regions includes therein a plurality of first openings disposed in the same arrangement, some of the plurality of first openings are first element forming openings each provided with a first compound semiconductor on which an electronic element is to be formed, and the other of the plurality of first openings are first dummy openings in which no electronic element is to be formed.

Abstract translation: 半导体晶片包括：基底晶片; 以及抑制层，其一体地设置在所述基底晶片上或者彼此分离，并且抑制化合物半导体的晶体的生长，其中所述抑制层具有多个第一开口区域，所述第一开口区域具有多个 穿过所述抑制层并通向所述基底晶片的开口，所述多个第一开口区域中的每一个在其中包括设置在相同布置中的多个第一开口，所述多个第一开口中的一些是第一元件形成开口，每个元件形成开口设置有第一 其上形成有电子元件的复合半导体，并且多个第一开口中的另一个是其中不形成电子元件的第一虚拟开口。

公开(公告)号：US20110316043A1

公开(公告)日：2011-12-29

申请号：US13062022

申请日：2009-09-16

Applicant: John Kouvetakis ,  Jose Menendez

Inventor： John Kouvetakis ,  Jose Menendez

IPC: H01L29/12 ,  H01L21/20

CPC classification number: H01L21/02381 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/02452 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/02573 ,  H01L21/0262

Abstract: Thin group IV semiconductor structures are provided comprising a thin Si substrate and a second region formed directly on the Si substrate, where the second region comprises either (i) a Ge1-xSnx layer; or (ii) a Ge layer having a threading dislocation density of less than about 105/cm2, and the effective bandgap of the second region is less than the effective bandgap of the Si substrate. Further, methods for preparing the thin group IV semiconductor structures are provided. Such structures are useful, for example, as components of solar cells.

Abstract translation: 提供了薄IV族半导体结构，其包括薄Si衬底和直接形成在Si衬底上的第二区域，其中第二区域包括（i）Ge1-xSnx层; 或（ii）穿透位错密度小于约105 / cm2的Ge层，并且第二区域的有效带隙小于Si衬底的有效带隙。 此外，提供了制备薄IV族半导体结构的方法。 这样的结构例如作为太阳能电池的组件是有用的。

公开(公告)号：US07598513B2

公开(公告)日：2009-10-06

申请号：US10559979

申请日：2004-06-14

Applicant: John Kouvetakis ,  Matthew Bauer ,  John Tolle

Inventor： John Kouvetakis ,  Matthew Bauer ,  John Tolle

IPC: H01L29/06 ,  H01L21/336

CPC classification number: H01L31/028 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02452 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/0259 ,  H01L21/0262 ,  H01L29/161 ,  H01L29/165 ,  Y02E10/547 ,  Y10S148/169 ,  Y10S438/936

Abstract: A novel method for synthesizing device-quality alloys and ordered phases in a Si—Ge—Sn system uses a UHV-CVD process and reactions of SnD4 with SiH3GeH3. Using the method, single-phase SixSnyGe1-x-y semiconductors (x≦0.25, y≦0.11) are grown on Si via Ge1-xSnx buffer layers The Ge1-xSnx buffer layers facilitate heteroepitaxial growth of the SixSnyGe1-x-y films and act as compliant templates that can conform structurally and absorb the differential strain imposed by the more rigid Si and Si—Ge—Sn materials. The SiH3GeH3 species was prepared using a new and high yield method that provided high purity semiconductor grade material.

Abstract translation: 在Si-Ge-Sn系统中合成器件质量合金和有序相的新方法使用特高压CVD法和SnD4与SiH3GeH3的反应。 使用该方法，通过Ge1-xSnx缓冲层在Si上生长单相SixSnyGe1-xy半导体（x <= 0.25，y <= 0.11）。Ge1-xSnx缓冲层促进SixSnyGe1-xy膜的异质外延生长，并作为 可以在结构上符合并吸收由更刚性的Si和Si-Ge-Sn材料施加的微分应变。 使用提供高纯度半导体级材料的新的高产率方法制备SiH 3 GeH 3物质。