公开(公告)号：US10079232B2

公开(公告)日：2018-09-18

申请号：US15463821

申请日：2017-03-20

申请人： International Business Machines Corporation

发明人： Veeraraghavan S Basker ,  Kangguo Cheng ,  Theodorus E Standaert ,  Junli Wang

IPC分类号： H01L27/092 ,  H01L29/78 ,  H01L21/225

CPC分类号： H01L27/0922 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/2255 ,  H01L21/3081 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/823892 ,  H01L21/845 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/1083 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7851

摘要： An advanced FinFET structure is described. A FinFET device includes a set of n-type FinFET devices and a set of p-type FinFET devices disposed on a substrate. The set of n-type FinFET devices have silicon channels and the set of p-type FinFET devices have silicon germanium channels. A set of punchthrough stop isolation regions are disposed under and isolate the n-type FinFET devices. A set of oxide isolation regions are disposed under and isolate the set of p-type FinFET devices.

公开(公告)号：US20180254333A1

公开(公告)日：2018-09-06

申请号：US15971225

申请日：2018-05-04

申请人： International Business Machines Corporation

发明人： Veeraraghavan S. Basker ,  Pouya Hashemi ,  Shogo Mochizuki ,  Alexander Reznicek

IPC分类号： H01L29/66 ,  H01L21/84 ,  H01L29/20 ,  H01L21/762 ,  H01L29/78 ,  H01L29/06

CPC分类号： H01L29/66795 ,  H01L21/76224 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/20 ,  H01L29/267 ,  H01L29/408 ,  H01L29/41766 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851

摘要： The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a fin using double trench epitaxy. The fin may be composed of a III-V semiconductor material and may be grown on a silicon, silicon germanium, or germanium substrate. A double trench aspect ratio trapping (ART) epitaxy method may trap crystalline defects within a first trench (i.e. a defective region) and may permit formation of a fin free of patterning defects in an upper trench (i.e. a fin mold). Crystalline defects within the defective region may be trapped via conventional aspect ratio trapping or three-sided aspect ratio trapping. Fin patterning defects may be avoided by utilizing a fin mold to grow an epitaxial fin and selectively removing dielectric material adjacent to a fin region.

公开(公告)号：US10062690B2

公开(公告)日：2018-08-28

申请号：US15209662

申请日：2016-07-13

申请人： STMICROELECTRONICS, INC.

发明人： Qing Liu ,  Prasanna Khare ,  Nicolas Loubet

IPC分类号： H01L29/76 ,  H01L21/336 ,  H01L27/088 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L21/265 ,  H01L29/417 ,  H01L21/225 ,  H01L21/8234

CPC分类号： H01L27/0886 ,  H01L21/2253 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785

摘要： A multi-fin FINFET device may include a substrate and a plurality of semiconductor fins extending upwardly from the substrate and being spaced apart along the substrate. Each semiconductor fin may have opposing first and second ends and a medial portion therebetween, and outermost fins of the plurality of semiconductor fins may comprise an epitaxial growth barrier on outside surfaces thereof. The FINFET may further include at least one gate overlying the medial portions of the semiconductor fins, a plurality of raised epitaxial semiconductor source regions between the semiconductor fins adjacent the first ends thereof, and a plurality of raised epitaxial semiconductor drain regions between the semiconductor fins adjacent the second ends thereof.

公开(公告)号：US20180233503A1

公开(公告)日：2018-08-16

申请号：US15825088

申请日：2017-11-28

申请人： International Business Machines Corporation

发明人： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC分类号： H01L27/092 ,  H01L23/528 ,  H01L21/8238 ,  H01L29/417 ,  H01L29/66 ,  H01L27/082 ,  H01L29/78 ,  H01L29/06

CPC分类号： H01L27/092 ,  H01L21/823431 ,  H01L21/823487 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/823871 ,  H01L21/823885 ,  H01L21/845 ,  H01L23/528 ,  H01L27/082 ,  H01L27/0924 ,  H01L27/11273 ,  H01L29/0649 ,  H01L29/41741 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/66795 ,  H01L29/7788 ,  H01L29/7802 ,  H01L29/7827 ,  H01L29/783 ,  H01L29/785 ,  H01L29/7853

摘要： CMOS inverters including gate-all-around vertical transistors are fabricated without requiring center gate contacts, thereby allowing close positioning of the transistors. The gate contact and the drain contact of the transistors are shared. Wiring of inverter input, output and power supply lines is simplified.

公开(公告)号：US10037994B2

公开(公告)日：2018-07-31

申请号：US15789488

申请日：2017-10-20

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tung Ying Lee ,  Wen-Huei Guo ,  Chih-Hao Chang ,  Shou-Zen Chang

IPC分类号： H01L27/088 ,  H01L27/06 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/66

CPC分类号： H01L27/0886 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0629 ,  H01L29/0642 ,  H01L29/66636 ,  H01L29/6681

摘要： Semiconductor devices and manufacturing and design methods thereof are disclosed. In one embodiment, a semiconductor device includes an active FinFET disposed over a workpiece comprising a first semiconductive material, the active FinFET comprising a first fin. An electrically inactive FinFET structure is disposed over the workpiece proximate the active FinFET, the electrically inactive FinFET comprising a second fin. A second semiconductive material is disposed between the first fin and the second fin.

公开(公告)号：US10037916B2

公开(公告)日：2018-07-31

申请号：US15464028

申请日：2017-03-20

申请人： International Business Machines Corporation

发明人： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Theodorus E. Standaert

IPC分类号： H01L21/8234 ,  H01L21/306 ,  H01L21/02 ,  H01L29/161 ,  H01L21/84 ,  H01L21/308 ,  H01L27/088 ,  H01L27/12

CPC分类号： H01L21/823431 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/02645 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/324 ,  H01L21/823412 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/1037 ,  H01L29/161 ,  H01L29/36 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

摘要： A method of forming a semiconductor structure includes providing a semiconductor substrate, forming at least one precursor semiconductor fin from the semiconductor substrate, etching through at least a portion of the at least one precursor semiconductor fin to form at least one patterned precursor semiconductor fin having a gap therein. The at least one patterned precursor semiconductor fin includes a first vertical surface and a second vertical surface with the gap therebetween. In addition, the method further includes forming a semiconductor material in the gap of the at least one patterned precursor semiconductor fin, in which the first vertical surface and the second vertical surface laterally surround the semiconductor material, and transforming the at least one patterned precursor semiconductor fin into at least one semiconductor fin including the semiconductor material therein.

公开(公告)号：US10037915B1

公开(公告)日：2018-07-31

申请号：US15700171

申请日：2017-09-10

申请人： UNITED MICROELECTRONICS CORP.

发明人： Te-Chang Hsu ,  Chun-Chia Chen ,  Yao-Jhan Wang

IPC分类号： H01L21/8234 ,  H01L29/78

CPC分类号： H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

摘要： A fabricating method of a semiconductor structure includes providing a substrate divided into a dense region and an isolated region, wherein a first gate structure is disposed within the dense region, and a second gate structure is disposed within the isolated region. Then, a first material layer is formed to cover the first gate structure, the second gate structure and the substrate. Later, a second material layer is formed to cover the first material layer. After that, the second material layer within the dense region is entirely removed. Subsequently, a third material layer is formed to cover the isolated region and the dense region. Next, the substrate is etched to forma first recess at two sides of the first gate structure, and a second recess at two sides of the second gate structure. Finally, an epitaxial layer is formed to fill the first recess and the second recess.

公开(公告)号：US20180212066A1

公开(公告)日：2018-07-26

申请号：US15923890

申请日：2018-03-16

申请人： International Business Machines Corporation

发明人： Kangguo CHENG ,  Bruce B. DORIS ,  Pouya HASHEMI ,  Ali KHAKIFIROOZ ,  Alexander REZNICEK

IPC分类号： H01L29/786 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/02 ,  H01L29/66 ,  H01L29/423 ,  H01L29/10 ,  H01L27/108 ,  H01L27/12 ,  H01L27/088 ,  H01L21/84

CPC分类号： H01L29/78696 ,  H01L21/02233 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/3081 ,  H01L21/3105 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7853

摘要： Non-planar semiconductor devices including semiconductor fins or stacked semiconductor nanowires that are electrostatically enhanced are provided. The electrostatic enhancement is achieved in the present application by epitaxially growing a semiconductor material protruding portion on exposed sidewalls of alternating semiconductor material portions of at least one hard mask capped semiconductor-containing fin structure that is formed on a substrate.

公开(公告)号：US20180204933A1

公开(公告)日：2018-07-19

申请号：US15920384

申请日：2018-03-13

申请人： STMICROELECTRONICS, INC.

发明人： John H. Zhang

IPC分类号： H01L29/66 ,  H01L27/12 ,  H01L21/84 ,  H01L29/78

CPC分类号： H01L29/66795 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/7845 ,  H01L29/785

摘要： Stress is introduced into the channel of an SOI FinFET device by transfer directly from a metal gate. In SOI devices in particular, stress transfer efficiency from the metal gate to the channel is nearly 100%. Either tensile or compressive stress can be applied to the fin channel by choosing different materials to be used in the gate stack as the bulk gate material, a gate liner, or a work function material, or by varying processing parameters during deposition of the gate or work function materials. P-gates and N-gates are therefore formed separately. Gate materials suitable for use as stressors include tungsten (W) for NFETs and titanium nitride (TiN) for PFETs. An optical planarization material assists in patterning the stress-inducing metal gates. A simplified process flow is disclosed in which isolation regions are formed without need for a separate mask layer, and gate sidewall spacers are not used.

公开(公告)号：US20180204837A1

公开(公告)日：2018-07-19

申请号：US15923097

申请日：2018-03-16

申请人： International Business Machines Corporation

发明人： Kangguo Cheng ,  Balasubramanian Pranatharthiharan ,  Alexander Reznicek ,  Charan V. Surisetty

IPC分类号： H01L27/088 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H01L29/49 ,  H01L29/423 ,  H01L29/417 ,  H01L29/08 ,  H01L29/06 ,  H01L27/12 ,  H01L27/108 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/8234

CPC分类号： H01L27/0886 ,  H01L21/28035 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/42376 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7855

摘要： The present invention relates generally to semiconductors, and more particularly, to a structure and method of minimizing shorting between epitaxial regions in small pitch fin field effect transistors (FinFETs). In an embodiment, a dielectric region may be formed in a middle portion of a gate structure. The gate structure be formed using a gate replacement process, and may cover a middle portion of a first fin group, a middle portion of a second fin group and an intermediate region of the substrate between the first fin group and the second fin group. The dielectric region may be surrounded by the gate structure in the intermediate region. The gate structure and the dielectric region may physically separate epitaxial regions formed on the first fin group and the second fin group from one another.