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    Interconnect structure
    43.
    发明申请
    Interconnect structure 失效
    互连结构

    公开(公告)号：US20020037656A1

    公开(公告)日：2002-03-28

    申请号：US09955302

    申请日：2001-09-19

    Inventor： Yoshinori Murakami

    IPC: H05K001/00

    CPC classification number: H05K3/368 ,  H01L2224/48091 ,  H01L2224/49111 ,  H01L2924/13091 ,  H01R12/52 ,  H05K1/0216 ,  H05K1/145 ,  H05K1/148 ,  H05K1/162 ,  H05K3/36 ,  H05K2201/0792 ,  H05K2201/09672 ,  H05K2201/1028 ,  H05K2201/10818 ,  H05K2201/10893 ,  H01L2924/00014 ,  H01L2924/00

    Abstract: An interconnect structure has a plurality of planar interconnects (1, 2) mutually superposed with a prescribed distance therebetween and serving as interconnects between two circuit boards (A, B), each of the planar interconnects (1, 2) having at least two connection terminals (1A, 1B, 2A, 2B) at the circuit boards (1, 2). Rather than using rigid wire interconnects as done in the past to make interconnections, planar interconnects having relatively large surface areas are used to increase the line-to-line capacitance, thereby enhancing the filtering function that reduces high-frequency noise.

    Abstract translation: 互连结构具有多个平面互连（1,2），它们之间以规定距离相互重叠并且用作两个电路板（A，B）之间的互连，每个平面互连（1,2）具有至少两个连接 电路板（1,2）上的端子（1A，1B，2A，2B）。 不像以前那样使用刚性的电线互连来做互连，而是使用具有相对大的表面积的平面互连来增加线对线电容，从而增强降低高频噪声的滤波功能。

    Split via surface mount connector and related techniques
    44.
    发明授权
    Split via surface mount connector and related techniques 失效
    通过表面贴装连接器和相关技术拆分

    公开(公告)号：US6137064A

    公开(公告)日：2000-10-24

    申请号：US359849

    申请日：1999-07-23

    Applicant: Sepehr Kiani ,  R. Ryan Vallance

    Inventor： Sepehr Kiani ,  R. Ryan Vallance

    IPC: H01R12/51 ,  H05K1/02 ,  H05K1/11 ,  H05K3/04 ,  H05K3/30 ,  H05K3/34 ,  H05K3/40 ,  H05K3/42 ,  H01R12/04

    CPC classification number: H05K1/0222 ,  H05K1/112 ,  H05K1/115 ,  H05K3/403 ,  H01R12/523 ,  H05K2201/09645 ,  H05K2201/1059 ,  H05K2201/10856 ,  H05K2201/10893 ,  H05K2201/10969 ,  H05K2203/0455 ,  H05K3/043 ,  H05K3/308 ,  H05K3/3421 ,  H05K3/429

    Abstract: An interconnection circuit includes a plated through hole having a plurality of electrically isolated segments with at least one of the plurality of electrically isolated segments coupled to a signal path and at least one of the electrically isolated segments coupled to ground. With this arrangement, the circuit provides a signal path between a first and a second different layers of a multilayer. By providing one segment as a signal segment and another segment as a ground segment the size and shape of the electrically isolated segments can be selected to provide the interconnection circuit having a predetermined impedance characteristic. The interconnection circuit can thus be impedance matched to circuit board circuits, devices and transmission lines, such as striplines, microstrips and co-planar waveguides. This results in an interconnection circuit which maintains the integrity of relatively high-frequency signals propagating through the interconnection circuit from the first layer to the second layer. The interconnect circuits can be formed by creating distinct conductor paths within the cylindrical plated through-holes using variety of manufacturing techniques including, but not limited to, broaching techniques, electrical discharge milling (EDM) techniques and laser etching techniques.

    Abstract translation: 互连电路包括具有多个电隔离段的电镀通孔，其中所述多个电隔离段中的至少一个耦合到信号路径和耦合到地的电隔离段中的至少一个。 利用这种布置，电路提供了多层的第一和第二不同层之间的信号路径。 通过将一个段作为信号段，另一个段作为接地段，可以选择电隔离段的大小和形状，以提供具有预定阻抗特性的互连电路。 因此，互连电路可以与电路板电路，器件和传输线（例如带状线，微带和共面波导）阻抗匹配。 这导致互连电路，其维持通过互连电路从第一层传播到第二层的相对高频信号的完整性。 可以通过使用各种制造技术（包括但不限于拉削技术，放电铣削（EDM）技术和激光蚀刻技术）在圆柱形电镀通孔内产生不同的导体路径来形成互连电路。

    Multilayer interconnection board and connection pin
    45.
    发明授权
    Multilayer interconnection board and connection pin 失效
    多层互连板和连接引脚

    公开(公告)号：US5975913A

    公开(公告)日：1999-11-02

    申请号：US50889

    申请日：1998-03-31

    Applicant: Shigehito Wada ,  Hisashi Saitou ,  Kazutoshi Morishima

    Inventor： Shigehito Wada ,  Hisashi Saitou ,  Kazutoshi Morishima

    IPC: H05K3/46 ,  H01R9/28 ,  H04Q1/14 ,  H05K1/00 ,  H05K1/11 ,  H05K3/40 ,  H01R29/00

    CPC classification number: H04Q1/145 ,  H01R9/28 ,  H04Q1/147 ,  H05K3/4046 ,  H05K1/0286 ,  H05K2201/09645 ,  H05K2201/10893

    Abstract: The interconnection board includes a plurality of non-conductive insulation layers and through-holes running through the insulation layers. A plurality of conductive patterns are provided on each insulation layer, electrically insulated from each other, and exposed to the inside of one through-hole at the same axial position of the through-hole. The connection pin has a non-conductive stem and a connection pattern provided on the non-conductive stem. The connection pattern extends in the axial direction of the connection pin and electrically connects two conductive patterns provided on different insulation layers at the same circumferential position in the through-hole, by bringing the conductive patterns into contact at positions which are axially different and circumferentially the same.

    Abstract translation: 互连板包括穿过绝缘层的多个非导电绝缘层和通孔。 多个导电图案设置在每个绝缘层上，彼此电绝缘，并且在通孔的相同轴向位置处暴露于一个通孔的内部。 连接销具有非导电杆和设置在非导电杆上的连接图案。 连接图案沿着连接销的轴向方向延伸，并且通过使导电图案在轴向不同并沿周向的位置接触地电连接设置在通孔中相同圆周位置处的不同绝缘层上的两个导电图案 相同。

    Multi-board electronic assembly including spacer for multiple electrical interconnections
    46.
    发明授权
    Multi-board electronic assembly including spacer for multiple electrical interconnections 失效
    多板电子组件，包括用于多个电互连的间隔件

    公开(公告)号：US5825633A

    公开(公告)日：1998-10-20

    申请号：US740940

    申请日：1996-11-05

    Applicant: C. Gregory Bujalski ,  Jeffrey M. Petsinger ,  Daniel T. Rooney

    Inventor： C. Gregory Bujalski ,  Jeffrey M. Petsinger ,  Daniel T. Rooney

    IPC: H05K3/34 ,  H05K3/36 ,  H05K1/11

    CPC classification number: H05K3/368 ,  H01R12/523 ,  H05K2201/09063 ,  H05K2201/10893 ,  H05K3/3442

    Abstract: A multi-board electronic assembly (10) includes a first substrate (12) and a second substrate (14) electrically connected by a spacer (16). The spacer (16) includes a first end (26) that is received in a first receptacle (18) on the first substrate (12) and a second end (28) that is received in a second receptacle (22) in the second substrate (14). The spacer (16) is formed generally of a nonconductive body (15) and includes ridges (60) and longitudinal channels (30) defined between the ridges (60). The ridges (60) are formed generally of a nonconductive material, and the spacer (16) includes a metallic strip (32) disposed within the channel (30). The metallic strip (32) forms a conductive path to connect the first circuit trace (20) to the second circuit trace (24) to form an electrically connected microelectronic assembly (10).

    Abstract translation: 多板电子组件（10）包括通过间隔件（16）电连接的第一基板（12）和第二基板（14）。 间隔件（16）包括容纳在第一基板（12）上的第一容器（18）中的第一端（26）和容纳在第二基板（22）中的第二容器（22）中的第二端 （14）。 间隔物（16）通常由非导电体（15）形成，并且包括限定在脊（60）之间的脊（60）和纵向通道（30）。 脊（60）通常由非导电材料形成，并且间隔件（16）包括设置在通道（30）内的金属条（32）。 金属条（32）形成导电路径以将第一电路迹线（20）连接到第二电路迹线（24）以形成电连接的微电子组件（10）。

    Method of manufacturing an apparatus having inner layers supporting surface-mount components
    47.
    发明授权
    Method of manufacturing an apparatus having inner layers supporting surface-mount components 失效
    制造具有支撑表面安装部件的内层的装置的方法

    公开(公告)号：US5659953A

    公开(公告)日：1997-08-26

    申请号：US464384

    申请日：1995-06-05

    Applicant: Stanford W. Crane, Jr. ,  Maria M. Portuondo

    Inventor： Stanford W. Crane, Jr. ,  Maria M. Portuondo

    IPC: H05K1/18 ,  H01L23/498 ,  H05K1/11 ,  H05K3/30 ,  H05K3/32 ,  H05K3/34 ,  H05K3/46 ,  H01R9/00 ,  H05K3/00

    CPC classification number: H01L23/49861 ,  H01L23/49811 ,  H05K1/112 ,  H05K3/308 ,  H05K3/3421 ,  H05K3/4623 ,  H01L2924/0002 ,  H05K2201/09472 ,  H05K2201/09536 ,  H05K2201/09645 ,  H05K2201/10189 ,  H05K2201/1031 ,  H05K2201/10318 ,  H05K2201/10704 ,  H05K2201/10772 ,  H05K2201/10893 ,  H05K3/321 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T29/49126 ,  Y10T29/49147 ,  Y10T29/49149

    Abstract: An apparatus comprising a multi-layer substrate including a plurality of layers of insulative material, at least one well formed in at least one of the layers, the well extending from an outer surface of the multi-layer substrate to an inner surface of the multi-layer substrate, and an electrically conductive component formed within the well on the inner surface of the multi-layer substrate; and a device having at least one electrically conductive lead or wire extending into the well and being in direct physical contact with the electrically conductive component formed on the inner surface of the multi-layer substrate. Also, a method of manufacturing an apparatus comprising the steps of forming a multi-layer substrate including a plurality of layers of insulative material, at least one well formed in at least one of the layers, the well extending from an outer surface of the multi-layer substrate to an inner surface of the multi-layer substrate, and an electrically conductive component formed within the well on the inner surface of the multi-layer substrate; and extending at least one electrically conductive lead or wire from a device into the well such that the lead or wire is in direct physical contact with the electrically conductive component formed on the inner surface of the multi-layer substrate.

    Abstract translation: 一种包括多层衬底的装置，所述多层衬底包括多层绝缘材料，至少一个阱形成在至少一层中，所述阱从所述多层衬底的外表面延伸到所述多层衬底的内表面 以及在所述多层基板的内表面上的所述阱内形成的导电部件; 以及具有延伸到阱中的至少一个导电引线或导线并与形成在多层基板的内表面上的导电部件直接物理接触的器件。 另外，制造装置的方法包括以下步骤：形成包括多层绝缘材料的多层基板，至少一层形成在至少一层中的阱，所述阱从所述多层的外表面延伸 在多层基板的内表面上形成有在多层基板的内表面上的导电部件， 并且将至少一个导电引线或线从器件延伸到阱中，使得引线或引线与形成在多层衬底的内表面上的导电部件直接物理接触。

    Apparatus having inner layers supporting surface-mount components
    48.
    发明授权
    Apparatus having inner layers supporting surface-mount components 失效
    具有支撑表面安装部件的内层的装置

    公开(公告)号：US5543586A

    公开(公告)日：1996-08-06

    申请号：US208519

    申请日：1994-03-11

    Applicant: Stanford W. Crane, Jr. ,  Maria M. Portuondo

    Inventor： Stanford W. Crane, Jr. ,  Maria M. Portuondo

    IPC: H05K1/18 ,  H01L23/498 ,  H05K1/11 ,  H05K3/30 ,  H05K3/32 ,  H05K3/34 ,  H05K3/46 ,  H05K1/02

    CPC classification number: H01L23/49861 ,  H01L23/49811 ,  H05K1/112 ,  H05K3/308 ,  H05K3/3421 ,  H05K3/4623 ,  H01L2924/0002 ,  H05K2201/09472 ,  H05K2201/09536 ,  H05K2201/09645 ,  H05K2201/10189 ,  H05K2201/1031 ,  H05K2201/10318 ,  H05K2201/10704 ,  H05K2201/10772 ,  H05K2201/10893 ,  H05K3/321 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T29/49126 ,  Y10T29/49147 ,  Y10T29/49149

    Abstract: An apparatus comprising a multi-layer substrate including a plurality of layers of insulative material, at least one well formed in at least one of the layers, the well extending from an outer surface of the multi-layer substrate to an inner surface of the multi-layer substrate, and an electrically conductive component formed within the well on the inner surface of the multi-layer substrate; and a device having at least one electrically conductive lead or wire extending into the well and being in direct physical contact with the electrically conductive component formed on the inner surface of the multi-layer substrate. Also, a method of manufacturing an apparatus comprising the steps of forming a multi-layer substrate including a plurality of layers of insulative material, at least one well formed in at least one of the layers, the well extending from an outer surface of the multi-layer substrate to an inner surface of the multi-layer substrate, and an electrically conductive component formed within the well on the inner surface of the multi-layer substrate; and extending at least one electrically conductive lead or wire from a device into the well such that the lead or wire is in direct physical contact with the electrically conductive component formed on the inner surface of the multi-layer substrate.

    Abstract translation: 一种包括多层衬底的装置，所述多层衬底包括多层绝缘材料，至少一个阱形成在至少一层中，所述阱从所述多层衬底的外表面延伸到所述多层衬底的内表面 以及形成在多层基板的内表面上的阱内的导电部件; 以及具有延伸到阱中的至少一个导电引线或导线并与形成在多层基板的内表面上的导电部件直接物理接触的器件。 另外，制造装置的方法包括以下步骤：形成包括多层绝缘材料的多层基板，至少一层形成在至少一层中的阱，所述阱从多层的外表面延伸 在多层基板的内表面上形成有在多层基板的内表面上的导电部件， 并且将至少一个导电引线或线从器件延伸到阱中，使得引线或引线与形成在多层衬底的内表面上的导电部件直接物理接触。

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