公开(公告)号：US5959340A

公开(公告)日：1999-09-28

申请号：US707815

申请日：1996-08-30

Applicant: Chang-Feng Wan ,  Richard Scott List ,  Curtis Gene Garrett ,  Dwight U. Bartholomew

Inventor： Chang-Feng Wan ,  Richard Scott List ,  Curtis Gene Garrett ,  Dwight U. Bartholomew

IPC: H01L21/58 ,  H01L31/00

CPC classification number: H01L24/83 ,  H01L24/29 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/0132 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/351

Abstract: This invention relates to mounting integrated circuits (IC) to multi-chip modules (MCM) or substrates. More specifically, it provides a method of mounting a semiconductor die such as a thin slice of Mercury Cadmium Telluride (MCT) to a silicon semiconductor substrate, a read-out integrated circuit (ROIC), using a thermoplastic to reduce stress on the MCT caused by mismatched Coefficients of Thermal Expansion (CTE). This process provides for an array of infrared photodetectors on a material such as MCT to be mounted to a read-out integrated circuit (ROIC) using the Vertical Integrated Photodiode (VIP) approach to FPAs, while allowing double sided interdiffusion of CdTe for surface passivation to reduce dark currents and improve performance, without the problems associated with mismatched coefficients of thermal expansion during high temperature processes.

公开(公告)号：US20110260319A1

公开(公告)日：2011-10-27

申请号：US13103267

申请日：2011-05-09

Applicant: Shriram Ramanathan ,  Patrick Morrow ,  Scott List ,  Michael Y. Chan ,  Mauro J. Kobrinsky ,  Sarah E. Kim ,  Kevin P. O'Brien ,  Michael C. Harmes ,  Thomas Marieb

Inventor： Shriram Ramanathan ,  Patrick Morrow ,  Scott List ,  Michael Y. Chan ,  Mauro J. Kobrinsky ,  Sarah E. Kim ,  Kevin P. O'Brien ,  Michael C. Harmes ,  Thomas Marieb

IPC: H01L23/498

CPC classification number: H01L24/16 ,  H01L24/11 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2224/8183 ,  H01L2224/81894 ,  H01L2224/81895 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/19041

Abstract: Three-dimensional stacked substrate arrangements with reliable bonding and inter-substrate protection.

Abstract translation: 具有可靠接合和衬底保护的三维堆叠衬底布置。

公开(公告)号：US07723208B2

公开(公告)日：2010-05-25

申请号：US10669205

申请日：2003-09-24

Applicant: Sarah E. Kim ,  R. Scott List ,  James G. Maveety ,  Alan M. Myers ,  Quat T. Vu

Inventor： Sarah E. Kim ,  R. Scott List ,  James G. Maveety ,  Alan M. Myers ,  Quat T. Vu

IPC: H01L21/30

CPC classification number: F04B19/006 ,  H01L23/473 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/00

Abstract: Trenches may be formed in the upper surfaces of a pair of wafers. Each trench may be coated with a catalyst that is capable of removing oxygen or hydrogen from a fluid used for cooling in a system making use of the electroosmotic effect for pumping. Channels may be formed to communicate fluid to and from the trench coated with the catalyst. The substrates may be combined in face-to-face abutment, for example using copper-to-copper bonding to form a re-combiner.

Abstract translation: 沟槽可以形成在一对晶片的上表面中。 每个沟槽可以涂覆有能够在利用用于泵送的电渗效应的系统中用于冷却的流体中除去氧气或氢气的催化剂。 可以形成通道以将流体与涂覆有催化剂的沟槽连通。 基板可以以面对面邻接方式组合，例如使用铜 - 铜键合来形成再组合器。

公开(公告)号：US20070284409A1

公开(公告)日：2007-12-13

申请号：US11844293

申请日：2007-08-23

Applicant: Mauro Kobrinsky ,  Shriram Ramanathan ,  Scott List

Inventor： Mauro Kobrinsky ,  Shriram Ramanathan ,  Scott List

IPC: H01L21/67

CPC classification number: H01L21/67092 ,  H01L21/76885 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L24/17 ,  H01L24/75 ,  H01L24/81 ,  H01L24/94 ,  H01L2224/0401 ,  H01L2224/05186 ,  H01L2224/05546 ,  H01L2224/05547 ,  H01L2224/0603 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/13022 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/16 ,  H01L2224/17 ,  H01L2224/75 ,  H01L2224/7511 ,  H01L2224/75252 ,  H01L2224/75314 ,  H01L2224/75315 ,  H01L2224/75317 ,  H01L2224/81011 ,  H01L2224/81012 ,  H01L2224/81013 ,  H01L2224/81121 ,  H01L2224/81209 ,  H01L2224/81801 ,  H01L2224/81895 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10158 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/3511

Abstract: The present invention discloses a method that includes: providing two wafers; forming raised contacts on the two wafers; aligning the two wafers; bringing together the raised contacts; locally deflecting the two wafers; and bonding the raised contacts. The present invention also discloses a bonded-wafer structure that includes: a first wafer, the first wafer being locally deflected, the first wafer including a first raised contact; and a second wafer, the second wafer being locally deflected, the second wafer including a second raised contact, wherein the second raised contact is bonded to the first raised contact.

Abstract translation: 本发明公开了一种方法，包括：提供两个晶片; 在两个晶片上形成凸起的接触; 对准两个晶片; 汇集联络人; 局部偏转两片晶片; 并且接合凸起的触点。 本发明还公开了一种接合晶片结构，其包括：第一晶片，所述第一晶片被局部偏转，所述第一晶片包括第一凸起接触; 和第二晶片，所述第二晶片局部偏转，所述第二晶片包括第二凸起接触件，其中所述第二凸起接触件接合到所述第一凸起接触件。

公开(公告)号：US07227257B2

公开(公告)日：2007-06-05

申请号：US10315565

申请日：2002-12-09

Applicant: Sarah E. Kim ,  R. Scott List ,  Alan Myers

Inventor： Sarah E. Kim ,  R. Scott List ,  Alan Myers

IPC: H01L23/34 ,  H01L23/10

CPC classification number: H01L23/473 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates generally to microelectronic technology, and more specifically, to an apparatus used for the cooling of active electronic devices utilizing micro-channels or micro-trenches, and a technique for fabricating the same.

Abstract translation: 本公开一般涉及微电子技术，更具体地，涉及用于利用微通道或微沟槽冷却有源电子器件的装置及其制造技术。

公开(公告)号：US07037804B2

公开(公告)日：2006-05-02

申请号：US10695328

申请日：2003-10-27

Applicant: Scot A. Kellar ,  Sarah E. Kim ,  R. Scott List

Inventor： Scot A. Kellar ,  Sarah E. Kim ,  R. Scott List

IPC: H01L21/30 ,  H01L21/46

CPC classification number: H01L25/50 ,  H01L21/185 ,  H01L21/743 ,  H01L21/76898 ,  H01L24/12 ,  H01L24/16 ,  H01L24/72 ,  H01L24/75 ,  H01L25/0657 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/13099 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/16 ,  H01L2224/2919 ,  H01L2224/75315 ,  H01L2224/81203 ,  H01L2224/81894 ,  H01L2224/81895 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/0665 ,  H01L2924/00014

Abstract: A three-dimensional (3-D) integrated chip system is provided with a first wafer including one or more integrated circuit (IC) devices; a second wafer including one or more integrated circuit (IC) devices; and a metal bonding layer deposited on opposing surfaces of the first and second wafers at designated locations to establish electrical connections between active IC devices on the first and second wafers and to provide metal bonding between the adjacent first and second wafers, when the first wafer is pressed against the second wafer using a flexible bladder press to account for height differences of the metal bonding layer across the opposing surfaces of the first and second wafers.

Abstract translation: 三维（3-D）集成芯片系统设置有包括一个或多个集成电路（IC）装置的第一晶片; 包括一个或多个集成电路（IC）装置的第二晶片; 以及在指定位置沉积在第一和第二晶片的相对表面上的金属粘结层，以在第一和第二晶片上的有源IC器件之间建立电连接，并且当第一晶片为 使用柔性膀胱压力机压在第二晶片上，以考虑穿过第一和第二晶片的相对表面的金属粘合层的高度差异。

公开(公告)号：US07034394B2

公开(公告)日：2006-04-25

申请号：US10682137

申请日：2003-10-08

Applicant: Shriram Ramanathan ,  Sarah E. Kim ,  R. Scott List ,  Gregory M. Chrysler

Inventor： Shriram Ramanathan ,  Sarah E. Kim ,  R. Scott List ,  Gregory M. Chrysler

IPC: H01L23/34

CPC classification number: H01L35/32 ,  H01L23/38 ,  H01L23/50 ,  H01L24/11 ,  H01L24/13 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L27/16 ,  H01L2224/05001 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48471 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/81801 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01015 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15312 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/4554

Abstract: A microelectronic assembly is provided, having thermoelectric elements formed on a die so as to pump heat away from the die when current flows through the thermoelectric elements. In one embodiment, the thermoelectric elements are integrated between conductive interconnection elements on an active side of the die. In another embodiment, the thermoelectric elements are on a backside of the die and electrically connected to a carrier substrate on a front side of the die. In a further embodiment, the thermoelectric elements are formed on a secondary substrate and transferred to the die.

公开(公告)号：US20050003650A1

公开(公告)日：2005-01-06

申请号：US10610743

申请日：2003-07-02

Applicant: Shriram Ramanathan ,  Patrick Morrow ,  Scott List ,  Michael Chan ,  Mauro Kobrinsky ,  Sarah Kim ,  Kevin O'Brien ,  Michael Harmes ,  Thomas Marieb

Inventor： Shriram Ramanathan ,  Patrick Morrow ,  Scott List ,  Michael Chan ,  Mauro Kobrinsky ,  Sarah Kim ,  Kevin O'Brien ,  Michael Harmes ,  Thomas Marieb

IPC: H01L21/60 ,  H01L21/98 ,  H01L25/065 ,  H01L21/44 ,  H01L21/48 ,  H01L23/02 ,  H01L23/48 ,  H01L23/52

CPC classification number: H01L24/16 ,  H01L24/11 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2224/8183 ,  H01L2224/81894 ,  H01L2224/81895 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/19041

Abstract: Three-dimensional stacked substrate arrangements with reliable bonding and inter-substrate protection.

Abstract translation: 具有可靠接合和衬底保护的三维堆叠衬底布置。

公开(公告)号：US07843036B2

公开(公告)日：2010-11-30

申请号：US12190550

申请日：2008-08-12

Applicant: Bruce A. Block ,  Richard Scott List

Inventor： Bruce A. Block ,  Richard Scott List

IPC: H01L21/00

CPC classification number: H01L28/87 ,  H01L27/0805

Abstract: An apparatus including a capacitor formed between metallization layers on a circuit, the capacitor including a bottom electrode coupled to a metal layer and a top electrode coupled to a metal via wherein the capacitor has a corrugated sidewall profile. A method including forming an interlayer dielectric including alternating layers of dissimilar dielectric materials in a multilayer stack over a metal layer of a device structure; forming a via having a corrugated sidewall; and forming a decoupling capacitor stack in the via that conforms to the sidewall of the via.

Abstract translation: 一种包括在电路上的金属化层之间形成的电容器的装置，所述电容器包括耦合到金属层的底部电极和耦合到金属通孔的顶部电极，其中所述电容器具有波纹侧壁轮廓。 一种方法，包括在器件结构的金属层上的多层堆叠中形成包含不同介电材料的交替层的层间电介质; 形成具有波形侧壁的通孔; 以及在通孔中形成去耦电容器叠层，其符合通孔的侧壁。

公开(公告)号：US07537954B2

公开(公告)日：2009-05-26

申请号：US11298280

申请日：2005-12-09

Applicant: Shriram Ramanathan ,  Sarah E. Kim ,  R. Scott List ,  Gregory M. Chrysler

Inventor： Shriram Ramanathan ,  Sarah E. Kim ,  R. Scott List ,  Gregory M. Chrysler

IPC: H01L27/16 ,  H01L21/70

CPC classification number: H01L35/32 ,  H01L23/38 ,  H01L23/50 ,  H01L24/11 ,  H01L24/13 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L27/16 ,  H01L2224/05001 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48471 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/81801 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01015 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15312 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/4554

Abstract: A microelectronic assembly is provided, having thermoelectric elements formed on a die so as to pump heat away from the die when current flows through the thermoelectric elements. In one embodiment, the thermoelectric elements are integrated between conductive interconnection elements on an active side of the die. In another embodiment, the thermoelectric elements are on a backside of the die and electrically connected to a carrier substrate on a front side of the die. In a further embodiment, the thermoelectric elements are formed on a secondary substrate and transferred to the die.