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    Method and apparatus for electrochemical plating semiconductor wafers
    52.
    发明授权
    Method and apparatus for electrochemical plating semiconductor wafers 有权
    电化学电镀半导体晶片的方法和装置

    公开(公告)号：US07988843B2

    公开(公告)日：2011-08-02

    申请号：US12705903

    申请日：2010-02-15

    Applicant: Chung-Liang Chang ,  Shau-Lin Shue

    Inventor： Chung-Liang Chang ,  Shau-Lin Shue

    IPC: C25D5/34

    CPC classification number: H01L21/2885 ,  C25D5/18 ,  C25D7/123 ,  C25D17/001 ,  C25D17/007 ,  H01L21/76877

    Abstract: A method of electroplating conductive material on semiconductor wafers controls undesirable surface defects by reducing the electroplating current as the wafer is being initially immersed in a plating bath. Further defect reduction and improved bottom up plating of vias is achieved by applying a static charge on the wafer before it is immersed in the bath, in order to enhance bath accelerators used to control the plating rate. The static charge is applied to the wafer using a supplemental electrode disposed outside the plating bath.

    Abstract translation: 在半导体晶片上电镀导电材料的方法通过在晶片最初浸入电镀槽中时减少电镀电流来控制不期望的表面缺陷。 通过在晶片浸入槽中之前对晶片施加静电电荷，以便增强用于控制电镀速率的浴加速器，可实现进一步的缺陷减少和改进的底部电镀通孔。 使用布置在电镀液外部的辅助电极将静电荷施加到晶片。

    Method and apparatus for electrochemical plating semiconductor wafers
    54.
    发明授权
    Method and apparatus for electrochemical plating semiconductor wafers 有权
    电化学电镀半导体晶片的方法和装置

    公开(公告)号：US07704368B2

    公开(公告)日：2010-04-27

    申请号：US11043601

    申请日：2005-01-25

    Applicant: Chung-Liang Chang ,  Shau-Lin Shue

    Inventor： Chung-Liang Chang ,  Shau-Lin Shue

    IPC: C25D7/12

    CPC classification number: H01L21/2885 ,  C25D5/18 ,  C25D7/123 ,  C25D17/001 ,  C25D17/007 ,  H01L21/76877

    Abstract: A method of electroplating conductive material on semiconductor wafers controls undesirable surface defects by reducing the electroplating current as the wafer is being initially immersed in a plating bath. Further defect reduction and improved bottom up plating of vias is achieved by applying a static charge on the wafer before it is immersed in the bath, in order to enhance bath accelerators used to control the plating rate. The static charge is applied to the wafer using a supplemental electrode disposed outside the plating bath.

    Abstract translation: 在半导体晶片上电镀导电材料的方法通过在晶片最初浸入电镀槽中时减少电镀电流来控制不期望的表面缺陷。 通过在晶片浸入槽中之前对晶片施加静电电荷，以便增强用于控制电镀速率的浴加速器，可实现进一步的缺陷减少和改进的底部电镀通孔。 使用布置在电镀液外部的辅助电极将静电荷施加到晶片。

    Silicide formation with a pre-amorphous implant
    55.
    发明授权
    Silicide formation with a pre-amorphous implant 有权
    具有预非晶态植入物的硅化物形成

    公开(公告)号：US07625801B2

    公开(公告)日：2009-12-01

    申请号：US11523678

    申请日：2006-09-19

    Applicant: Chii-Ming Wu ,  Cheng-Tung Lin ,  Chih-Wei Chang ,  Shau-Lin Shue

    Inventor： Chii-Ming Wu ,  Cheng-Tung Lin ,  Chih-Wei Chang ,  Shau-Lin Shue

    IPC: H01L21/336

    CPC classification number: H01L21/26506 ,  H01L21/2658 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/78654

    Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate, forming a gate stack on the semiconductor substrate, forming a silicon-containing compound stressor adjacent the gate stack, implanting non-siliciding ions into the silicon-containing compound stressor to amorphize an upper portion of the silicon-containing compound stressor, forming a metal layer on the silicon-containing compound stressor while the upper portion of the SiGe stressor is amorphous, and annealing to react the metal layer with the silicon-containing compound stressor to form a silicide region. The silicon-containing compound stressor includes SiGe or SiC.

    Abstract translation: 一种用于形成半导体结构的方法包括：提供半导体衬底，在半导体衬底上形成栅极叠层，在栅堆叠附近形成含硅化合物应力源，将非硅化离子注入到含硅化合物应力器中以使上层 含硅化合物应激源的部分，在含硅化合物应激物上形成金属层，同时SiGe应力源的上部是无定形的，退火使金属层与含硅化合物应激反应物形成硅化物区域 。 含硅化合物应激源包括SiGe或SiC。

    Sidewall coverage for copper damascene filling
    56.
    发明授权
    Sidewall coverage for copper damascene filling 有权
    铜镶嵌填料的侧壁覆盖

    公开(公告)号：US07514348B2

    公开(公告)日：2009-04-07

    申请号：US11860639

    申请日：2007-09-25

    Applicant: Shau-Lin Shue ,  Mei-Yun Wang ,  Chen-Hua Yu

    Inventor： Shau-Lin Shue ,  Mei-Yun Wang ,  Chen-Hua Yu

    IPC: H01L21/302

    CPC classification number: H01L21/76843 ,  H01L21/2855 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76874 ,  H01L2221/1089

    Abstract: A general process is described for filling a hole or trench at the surface of an integrated circuit without trapping voids within the filler material. A particular application is the filling of a trench with copper in order to form damascene wiring. First, a seed layer is deposited in the hole or trench by means of PVD. This is then followed by a sputter etching step which removes any overhang of this seed layer at the mouth of the trench or hole. A number of process variations are described including double etch/deposit steps, varying pressure and voltage in the same chamber to allow sputter etching and deposition to take place without breaking vacuum, and reduction of contact resistance between wiring levels by reducing via depth.

    Abstract translation: 描述了在集成电路的表面处填充孔或沟槽而不在填充材料内捕获空隙的一般方法。 具体应用是用铜填充沟槽以形成镶嵌线。 首先，通过PVD将种子层沉积在孔或沟槽中。 然后进行溅射蚀刻步骤，其移除沟槽或孔口处的该种子层的任何突出端。 描述了许多工艺变化，包括双重蚀刻/沉积步骤，在相同的室中改变压力和电压，以允许在不破坏真空的情况下进行溅射蚀刻和沉积，并且通过减小通孔深度来降低布线水平之间的接触电阻。

    Adhesion of copper and etch stop layer for copper alloy
    57.
    发明授权
    Adhesion of copper and etch stop layer for copper alloy 有权
    铜合金的附着力和蚀刻停止层

    公开(公告)号：US07443029B2

    公开(公告)日：2008-10-28

    申请号：US11201845

    申请日：2005-08-11

    Applicant: Jing Cheng Lin ,  Ching-Hua Hsieh ,  Shau-Lin Shue ,  Mong-Song Liang

    Inventor： Jing Cheng Lin ,  Ching-Hua Hsieh ,  Shau-Lin Shue ,  Mong-Song Liang

    IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC classification number: H01L21/76843 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76855 ,  H01L21/76864 ,  H01L21/76873 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A new method and structure is provided for the creation of a copper dual damascene interconnect. A dual damascene structure is created in the layer of dielectric, optionally a metal barrier layer is deposited over exposed surfaces of the dual damascene structure. A copper seed layer is deposited, the dual damascene structure is filled with copper. An anneal is applied to the created copper interconnect after which excess copper is removed from the dielectric. Of critical importance to the invention, a thin layer of oxide is then deposited as a cap layer over the copper dual damascene interconnect, an etch stop layer is then deposited over the thin layer of oxide for continued upper-level metallization.

    Abstract translation: 提供了一种新的方法和结构，用于创建铜双镶嵌互连。 在电介质层中产生双镶嵌结构，任选地，金属阻挡层沉积在双镶嵌结构的暴露表面上。 沉积铜籽晶层，双镶嵌结构填充铜。 对所制造的铜互连进行退火，之后从电介质去除多余的铜。 对本发明至关重要的是，然后在铜双镶嵌互连件上沉积薄层的氧化物作为覆盖层，然后将蚀刻停止层沉积在氧化物薄层上用于持续的上层金属化。

    Damascene interconnect structure with cap layer
    59.
    发明授权
    Damascene interconnect structure with cap layer 有权
    镶嵌互连结构与盖层

    公开(公告)号：US07259463B2

    公开(公告)日：2007-08-21

    申请号：US11004767

    申请日：2004-12-03

    Applicant: Jui Jen Huang ,  Minghsing Tsai ,  Shau-Lin Shue ,  Hung-Wen Su ,  Ting-Chu Ko

    Inventor： Jui Jen Huang ,  Minghsing Tsai ,  Shau-Lin Shue ,  Hung-Wen Su ,  Ting-Chu Ko

    IPC: H01L23/48

    CPC classification number: H01L21/76838 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76834 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of forming an integrated circuit interconnect structure is presented. A first conductive line is formed over a semiconductor substrate. A conductive cap layer is formed on the first conductive line to improve device reliability. An etch stop layer (ESL) is formed on the conductive cap layer. An inter-level dielectric (IMD) is formed on the ESL. A via opening and a trench are formed in the ESL, IMD, and conductive cap layer. A recess is formed in the first conductive line. The recess can be formed by over etching when the first dielectric is etched, or by a separate process such as argon sputtering. A second conductive line is formed filling the trench, opening and recess.

    Abstract translation: 提出了一种形成集成电路互连结构的方法。 在半导体衬底上形成第一导电线。 导电盖层形成在第一导电线上以提高器件的可靠性。 在导电盖层上形成蚀刻停止层（ESL）。 在ESL上形成层间电介质（IMD）。 通孔和沟槽形成在ESL，IMD和导电盖层中。 在第一导线中形成凹部。 当蚀刻第一电介质时，或者通过诸如氩气溅射的分离工艺，可以通过过蚀刻形成凹部。 形成第二导电线，填充沟槽，开口和凹陷。

    Method of forming contact plug on silicide structure
    60.
    发明授权
    Method of forming contact plug on silicide structure 有权
    在硅化物结构上形成接触塞的方法

    公开(公告)号：US07256137B2

    公开(公告)日：2007-08-14

    申请号：US11052938

    申请日：2005-02-07

    Applicant: Chii-Ming Wu ,  Chih-Wei Chang ,  Shau-Lin Shue ,  Ju-Wang Hsu ,  Ming-Huan Tsai

    Inventor： Chii-Ming Wu ,  Chih-Wei Chang ,  Shau-Lin Shue ,  Ju-Wang Hsu ,  Ming-Huan Tsai

    IPC: H01L21/302 ,  H01L21/461

    CPC classification number: H01L21/76829 ,  H01L21/31105 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76832

    Abstract: A method of manufacturing a semiconductor device is provided comprising the steps of: (a) forming a semiconductor element on a substrate, the semiconductor element having at least one nickel silicide contact region, a first etch stop layer formed over the element and an insulating layer formed over the first etch stop layer; (b) forming an opening through the insulating layer over the contact region at least to the first etch stop layer; (c) removing a portion of the first etch stop layer contacting a selected contact region using a process that does not substantially oxidize with the contact region, to form a contact opening to the contact region; and (d) filling the contact opening with conductive material to form a contact.

    Abstract translation: 提供一种制造半导体器件的方法，包括以下步骤：（a）在衬底上形成半导体元件，所述半导体元件具有至少一个硅化镍接触区域，形成在元件上的第一蚀刻停止层和绝缘层 形成在第一蚀刻停止层上; （b）至少在所述第一蚀刻停止层上在所述接触区域上形成穿过所述绝缘层的开口; （c）使用不与接触区域基本上氧化的工艺去除与所选择的接触区域接触的第一蚀刻停止层的一部分，以形成到接触区域的接触开口; 和（d）用导电材料填充接触开口以形成接触。

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