摘要:
Disclosed are a structure including alignment marks and a method of forming alignment marks in three dimensional (3D) structures. The method includes forming apertures in a first surface of a first semiconductor substrate; joining the first surface of the first semiconductor substrate to a first surface of a second semiconductor substrate; thinning the first semiconductor on a second surface of the first semiconductor substrate to provide optical contrast between the apertures and the first semiconductor substrate; and aligning a feature on the second surface of the first semiconductor substrate using the apertures as at least one alignment mark.
摘要:
A layer of polymer material is applied on a peripheral region of at least one of the two substrates to be bonded prior to bonding. The bonded structure formed thereby includes a first substrate, a second substrate in direct contact with the first substrate, and a ring of the polymer material in direct contact with the first substrate at a first interface and in direct contact with the second substrate. The ring of polymer material laterally surrounds and seals the interface at which the first substrate contacts the second substrate. A ring-shaped cavity can be formed within the polymeric ring. Alternately, the first interface and the second interface can be contiguous without a ring-shaped cavity between the first and second substrates.
摘要:
A method of forming wire bonds in (I/C) chips comprising: providing an I/C chip having a conductive pad for a wire bond with at least one layer of dielectric material overlying the pad; forming an opening through the dielectric material exposing a portion of said pad. Forming at least a first conductive layer on the exposed surface of the pad and on the surface of the opening. Forming a seed layer on the first conductive layer; applying a photoresist over the seed layer; exposing and developing the photoresist revealing the surface of the seed layer surrounding the opening; removing the exposed seed layer; removing the photoresist material in the opening revealing the seed layer. Plating at least one second layer of conductive material on the seed layer in the opening, and removing the first conductive layer on the dielectric layer around the opening. The invention also includes the resulting structure.
摘要:
Resistors that avoid the problems of miniaturization of semiconductor devices and a related method are disclosed. In one embodiment, a resistor includes a planar resistor material that extends vertically within at least one metal layer of a semiconductor device. In another embodiment, a resistor includes a resistor material layer extending between a first bond pad and a second bond pad of a semiconductor device. The two embodiments can be used alone or together. A related method for generating the resistors is also disclosed.
摘要:
Carriers (10) holding parts (50) for assembling complex MEMS devices are transported to a central assembly location. The parts are stacked in a pre-assigned order and later released from their carriers. Alternatively, they are positioned over the appropriate location and released so as to fall into position as needed. The assembly area (100) includes a cavity below the plane of the carriers such that the parts held within the carrier drop into the cavity. Heating elements are integrated into the cavity to assist in the release of the parts. The cavity is supplied with parts by one or more carriers which are move around by any number of MEMS drive systems (200, 250). The cavity and some of the MEMS assembled therein deliver with precision amounts of materials as required suitable for biomedical applications, or may be processed in-situ, as in an on-chip laboratory.
摘要:
Direct termination of a wiring metal in a semiconductor device. Direct termination of an AlCu stack or an AlCu layer is made with an underlying Cu wiring level. The AlCu stack or AlCu layer covers all of the Cu wiring level such that it has a border that extends beyond all of the wiring to prevent exposure from occurring.
摘要:
A three-dimensional package consisting of a plurality of folded integrated circuit chips (100, 110, 120) is described wherein at least one chip provides interconnect pathways for electrical connection to additional chips of the stack, and at least one chip (130) is provided with additional interconnect wiring to a substrate (500), package or printed circuit board. Further described, is a method of providing a flexible arrangement of interconnected chips that are folded over into a three-dimensional arrangements to consume less aerial space when mounted on a substrate, second-level package or printed circuit board.
摘要:
A passive electrical device includes a first electrical conductor, a second electrical conductor disposed over the first conductor; and a third electrical conductor connecting the first conductor to the second conductor. The said first, second and third conductors are disposed on a semiconductor substrate. The sheet resistivity of the first conductor is approximately equal to the sheet resistivity of the second conductor.
摘要:
A method and structure for a fuse structure comprises an insulator layer, a plurality of fuse electrodes extending through the insulator layer to an underlying wiring layer, an electroplated fuse element connected to the electrodes, and an interface wall. The fuse element is positioned external to the insulator, with a gap juxtaposed between the insulator and the fuse element. The interface wall further comprises a first side wall, a second side wall, and an inner wall, wherein the inner wall is disposed within the gap. The fuse electrodes are diametrically opposed to one another, and the fuse element is perpendicularly disposed above the fuse electrodes. The fuse element is either electroplatted, electroless plated, or is an ultra thin fuse.
摘要:
A laser-programmable fuse structure for an integrated circuit device is disclosed. In an exemplary embodiment of the invention, the fuse structure includes a conductive layer, the conductive layer completing a conductive path between wiring segments in a wiring layer. An organic material is encapsulated underneath the conductive layer, wherein the fuse structure is blown open by application of a beam of laser energy thereto.