公开(公告)号：US20060039721A1

公开(公告)日：2006-02-23

申请号：US10510755

申请日：2003-04-11

申请人： Yasuro Shiomura ,  Yuichiro Mori ,  Koji Yamakawa

发明人： Yasuro Shiomura ,  Yuichiro Mori ,  Koji Yamakawa

IPC分类号： G03G15/08

CPC分类号： G03G15/0808

摘要： In a conductive roller having a rotation shaft and a conductive elastic layer arranged around the rotation shaft, a resin coating layer including a particle having JIS A hardness of 10-99 and an average particle size of 2-30 μm. An image forming apparatus utilizes the conductive roller mentioned above. Herewith, the image forming apparatus, which has excellent toner carrying property and toner charge property, provides a high quality image with no image unevenness and no image overlapping, and has an excellent durability, and the image forming apparatus installing the above conductive roller are provided.

摘要翻译： 在具有旋转轴和布置在旋转轴周围的导电弹性层的导电辊中，具有JIS A硬度为10-99，平均粒径为2-30μm的颗粒的树脂涂层。 图像形成装置利用上述导电性辊。 因此，具有优异的调色剂携带性和调色剂带电性的图像形成装置提供了无图像不均匀，无图像重叠的高质量图像，并且具有优异的耐久性，并且设置安装上述导电辊的图像形成装置 。

公开(公告)号：US20060017086A1

公开(公告)日：2006-01-26

申请号：US11223958

申请日：2005-09-13

申请人： Hiroyuki Kanaya ,  Iwao Kunishima ,  Koji Yamakawa ,  Tsuyoshi Iwamoto ,  Hiroshi Mochizuki ,  Yoshinori Kumura

发明人： Hiroyuki Kanaya ,  Iwao Kunishima ,  Koji Yamakawa ,  Tsuyoshi Iwamoto ,  Hiroshi Mochizuki ,  Yoshinori Kumura

IPC分类号： H01L29/94

CPC分类号： H01L27/11502 ,  H01L27/11507 ,  H01L28/56 ,  H01L28/57 ,  H01L28/65

摘要： There is provided a semiconductor device having a ferroelectric capacitor formed on a semiconductor substrate covered with an insulator film, wherein the ferroelectric capacitor comprises: a bottom electrode formed on the insulator film; a ferroelectric film formed on the bottom electrode; and a top electrode formed on the ferroelectric film. The ferroelectric film has a stacked structure of either of two-layer-ferroelectric film or three-layer-ferroelectric film. The upper ferroelectric film is metallized and prevents hydrogen from diffusing in lower ferroelectric layer. Crystal grains of the stacked ferroelectric films are preferably different.

公开(公告)号：US06586790B2

公开(公告)日：2003-07-01

申请号：US09359324

申请日：1999-07-23

申请人： Hiroyuki Kanaya ,  Iwao Kunishima ,  Koji Yamakawa ,  Tsuyoshi Iwamoto ,  Hiroshi Mochizuki

发明人： Hiroyuki Kanaya ,  Iwao Kunishima ,  Koji Yamakawa ,  Tsuyoshi Iwamoto ,  Hiroshi Mochizuki

IPC分类号： H01L2976

CPC分类号： H01L27/11502 ,  H01L27/11507 ,  H01L28/56 ,  H01L28/57 ,  H01L28/65

摘要： There is provided a semiconductor device having a ferroelectric capacitor formed on a semiconductor substrate covered with an insulator film, wherein the ferroelectric capacitor comprises: a bottom electrode formed on the insulator film; a ferroelectric film formed on the bottom electrode; and a top electrode formed on the ferroelectric film. The ferroelectric film has a stacked structure of either of two-layer-ferroelectric film or three-layer-ferroelectric film. The upper ferroelectric film is metallized and prevents hydrogen from diffusing in lower ferroelectric layer. Crystal grains of the stacked ferroelectric films are preferably different.

摘要翻译： 提供一种半导体器件，其具有形成在被绝缘体膜覆盖的半导体衬底上的铁电电容器，其中所述强电介质电容器包括：形成在所述绝缘膜上的底部电极; 形成在底部电极上的铁电体膜; 以及形成在强电介质膜上的顶部电极。 铁电体膜具有两层铁电体膜或三层铁电体膜的层叠结构。 上部铁电膜被金属化，并防止氢在下部铁电层中扩散。 堆叠的铁电体膜的晶粒优选不同。

公开(公告)号：US5969413A

公开(公告)日：1999-10-19

申请号：US855931

申请日：1997-05-14

申请人： Keiichi Yano ,  Kazuo Kimura ,  Hironori Asai ,  Jun Monma ,  Koji Yamakawa ,  Mitsuyoshi Endo ,  Hirohisa Osoguchi

发明人： Keiichi Yano ,  Kazuo Kimura ,  Hironori Asai ,  Jun Monma ,  Koji Yamakawa ,  Mitsuyoshi Endo ,  Hirohisa Osoguchi

IPC分类号： H01L23/10 ,  H01L23/15 ,  H01L23/28 ,  H01L23/495 ,  H01L23/02 ,  H01L23/12 ,  H01L23/48

CPC分类号： H01L23/10 ,  H01L23/15 ,  H01L23/49572 ,  H01L24/50 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/30107

摘要： A semiconductor chip is supported on a tape carrier provided with lead wirings. The semiconductor chip is electrically connected to the lead wirings. The semiconductor chip of this quality is bonded in combination with the pe carrier to an aluminum nitride substrate. The lead wirings provided on the carrier combine the two functions as an internal lead and an external lead. The semiconductor package of such a structure as is described above allows multi-terminal connection by the narrowing of pitches between the leads and permits provision of a miniature package excelling in the heat-radiating property. Alternatively, the lead wirings supported on the tape carrier and electrically connected to the semiconductor chip are utilized as internal leads. For the external leads, such lead frames as are bonded to the aluminum nitride substrate are used. The lead frames are electrically connected to the internal leads provided in the tape carrier.

摘要翻译： 半导体芯片被支撑在带有引线配线的带载体上。 半导体芯片电连接到引线配线。 该质量的半导体芯片与pe载体结合到氮化铝衬底上。 载体上提供的导线结合了作为内部引线和外部引线的两个功能。 如上所述的这种结构的半导体封装允许通过引线之间的间距变窄来实现多端子连接，并且允许提供具有优异的散热性能的微型封装。 或者，支撑在带载体上并电连接到半导体芯片的引线配线被用作内部引线。 对于外部引线，使用与氮化铝基板结合的引线框架。 引线框架电连接到设置在带式载体中的内部引线。

公开(公告)号：US5907187A

公开(公告)日：1999-05-25

申请号：US502587

申请日：1995-07-14

申请人： Kaoru Koiwa ,  Koji Yamakawa ,  Kiyoshi Iyogi ,  Takaaki Yasumoto ,  Nobuo Iwase

发明人： Kaoru Koiwa ,  Koji Yamakawa ,  Kiyoshi Iyogi ,  Takaaki Yasumoto ,  Nobuo Iwase

IPC分类号： H01L23/498 ,  H05K3/34 ,  H01L23/48 ,  H01L23/06 ,  H01L23/52 ,  H01L29/40

CPC分类号： H05K3/3436 ,  H01L23/49816 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K2201/094 ,  H05K2201/10992 ,  H05K2203/041 ,  H05K3/3463 ,  H05K3/3484 ,  Y02P70/613

摘要： In such electronic components as semiconductor packages and semiconductor chips which are possessed of groups of connecting bumps as input and output terminals, the groups of connecting bumps comprise not less than two kinds of connecting bumps different in melting point or not less than two kinds of connecting bumps different in mechanical strength. The groups of connecting bumps comprise connecting bumps made of high temperature solder or connecting bumps made of a high strength In type solder in the part of formation thereof. The connecting bumps made of high temperature solder are not directly affected by the influence of displacement because they retain the shape of a ball even after the step of connection such as solder reflow. The connecting bumps made of In type solder form connecting parts of high strength. These groups of connecting bumps contribute to exalt the reliability of the connecting parts without decreasing the number of input and output terminals.

摘要翻译： 在具有作为输入和输出端子的连接凸块组的半导体封装和半导体芯片的这种电子部件中，连接凸块组包括不少于两种不同熔点的连接凸块或不少于两种连接 不同的机械强度凸起。 连接凸块的组包括在其形成部分中由高温焊料或由高强度In型焊料制成的连接凸块形成的连接凸块。 由高温焊料制成的连接凸块不受位移影响的直接影响，因为即使在诸如焊料回流的连接步骤之后，它们保持了球的形状。 由In型焊料形成的连接凸块形成高强度的连接部件。 这些连接凸块组有助于提高连接部件的可靠性，而不会减少输入和输出端子的数量。

公开(公告)号：US5821627A

公开(公告)日：1998-10-13

申请号：US962882

申请日：1997-11-05

申请人： Miki Mori ,  Yukio Kizaki ,  Takaaki Yasumoto ,  Koji Yamakawa ,  Masayuki Saito ,  Tatsuro Uchida ,  Takasi Togasaki ,  Takashi Yebisuya ,  Taijun Murakami

发明人： Miki Mori ,  Yukio Kizaki ,  Takaaki Yasumoto ,  Koji Yamakawa ,  Masayuki Saito ,  Tatsuro Uchida ,  Takasi Togasaki ,  Takashi Yebisuya ,  Taijun Murakami

IPC分类号： H05K3/32 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H05K3/328 ,  H01L2224/1134 ,  H01L2224/13109 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01025 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/19041 ,  H05K2201/10636 ,  H05K2201/10734 ,  Y02P70/611

摘要： An electronic circuit device includes a substrate, a wiring layer formed on the surface of the substrate and essentially consisting of at least one metal selected from the group consisting of gold, copper, tin, and aluminum, a bump formed on the wiring layer and essentially consisting of at least one metal selected from the group consisting of gold, copper, and aluminum, and a micro electronic element formed on the bump, wherein solid-phase diffusion bonding is performed at least either between the wiring layer and the bump or between the bump and an electrode of the micro electronic element.

摘要翻译： 电子电路装置包括：基板，形成在基板的表面上的基本上由布线层形成的凸块和基本上由金，铜，锡和铝组成的组中的至少一种金属组成的布线层; 由选自金，铜和铝的至少一种金属和形成在凸块上的微电子元件组成，其中固定相扩散接合至少在布线层和凸块之间或者在 凸块和微电子元件的电极。

公开(公告)号：US5400275A

公开(公告)日：1995-03-21

申请号：US712092

申请日：1991-06-07

申请人： Kazuhide Abe ,  Hiroshi Toyoda ,  Koji Yamakawa ,  Motomasa Imai ,  Koji Sakui

发明人： Kazuhide Abe ,  Hiroshi Toyoda ,  Koji Yamakawa ,  Motomasa Imai ,  Koji Sakui

IPC分类号： G11C11/22 ,  H01L27/115 ,  G11C7/00

CPC分类号： H01L27/11502 ,  G11C11/22

摘要： A semiconductor memory device comprises a plurality of memory cells arranged in the form of a matrix to constitute rows-and columns, a plurality of first driving lines, connected to the memory cells, for transmitting a first driving signal to the memory cells, one of the plurality of first driving lines being selected by a row address, a plurality of second driving lines, connected to the memory cells, for transmitting a second driving signal to the memory cells, one of the plurality of second driving lines being selected by a column address, a plurality of read/write lines, connected to the memory cells, for performing read/write operations with respect to the memory cells, and a plurality of sense amplifiers connected to the read/ write lines, wherein one of the plurality of sense amplifiers is selected by the column address, and the memory cells in the same column are connected to the same sense amplifier through the read/write lines.

摘要翻译： 一种半导体存储器件包括以矩阵形式布置以构成行和列的多个存储器单元，连接到存储器单元的多条第一驱动线，用于将第一驱动信号发送到存储器单元，其中之一 所述多个第一驱动线由行地址选择，多个第二驱动线连接到所述存储单元，用于将第二驱动信号发送到所述存储单元，所述多个第二驱动线中的一个由列选择 连接到存储器单元的多个读/写线，用于对存储单元执行读/写操作，以及连接到读/写线的多个读出放大器，其中多个感测中的一个 放大器由列地址选择，同一列中的存储单元通过读/写线连接到相同的读出放大器。

公开(公告)号：US5326623A

公开(公告)日：1994-07-05

申请号：US10298

申请日：1993-01-28

申请人： Koji Yamakawa ,  Kaoru Koiwa ,  Takaaki Yasumoto ,  Kiyoshi Iyogi ,  Nobuo Iwase

发明人： Koji Yamakawa ,  Kaoru Koiwa ,  Takaaki Yasumoto ,  Kiyoshi Iyogi ,  Nobuo Iwase

IPC分类号： C04B37/02 ,  H01L23/12 ,  H01L23/15 ,  H01L23/498 ,  H01L23/538 ,  H05K1/09 ,  H05K3/24 ,  B32B9/00

CPC分类号： H01L23/538 ,  H01L23/49866 ,  H01L2924/0002 ,  H01L2924/09701 ,  Y10S428/901 ,  Y10T428/24917 ,  Y10T428/24926

摘要： A circuit board including a circuit pattern adhered firmly to a ceramic substrate and capable of eliminating an increase in resistivity due to an influence of an external environment, particularly, a thermal influence is disclosed. The circuit board comprises a ceramic substrate, and a circuit pattern formed on the substrate and having a multilayered structure in which a bonding layer comprising Ti and at least one element selected from the group consisting of N and O, a conductor layer consisting essentially of Cu, and a protective layer comprising Ti and at least one element selected from the group consisting of N and O are stacked in the order named.

摘要翻译： 公开了一种电路板，其包括牢固地粘附在陶瓷基板上的电路图形，能够消除由外部环境的影响引起的电阻率的增加，特别是热影响。 电路板包括陶瓷基板和形成在基板上并具有多层结构的电路图案，其中包含Ti和至少一种选自N和O的元素的接合层，基本上由Cu组成的导体层 ，并且以所述顺序堆叠包含Ti和从N和O组成的组中选择的至少一种元素的保护层。

公开(公告)号：US5155573A

公开(公告)日：1992-10-13

申请号：US633324

申请日：1990-12-24

申请人： Kazuhide Abe ,  Hiroshi Toyoda ,  Koji Yamakawa ,  Motomasa Imai ,  Mitsuo Harata ,  Koji Sakui

发明人： Kazuhide Abe ,  Hiroshi Toyoda ,  Koji Yamakawa ,  Motomasa Imai ,  Mitsuo Harata ,  Koji Sakui

IPC分类号： H01L21/02 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/92

CPC分类号： H01L27/11502 ,  H01L27/11507 ,  H01L28/60

摘要： A ferroelectric capacitor includes a ferroelectric layer consisting of lead zirconate titanate formed on a silicon substrate, a plurality of rectangular trenches formed in the direction of thickness of the ferroelectric layer with a ferroelectric material therebetween, and first and second electrodes consisting of metal tungsten buried in the trenches to oppose each other with the ferroelectric material therebetween.

摘要翻译： 铁电电容器包括由在硅衬底上形成的锆钛酸铅构成的铁电层，在其间具有铁电体的铁电层的厚度方向上形成的多个矩形沟槽，以及埋入金属钨的第一和第二电极 沟槽之间用铁电材料彼此相对。

公开(公告)号：US4906341A

公开(公告)日：1990-03-06

申请号：US247619

申请日：1988-09-22

申请人： Koji Yamakawa ,  Kaoru Koiwa ,  Nobuo Iwase

发明人： Koji Yamakawa ,  Kaoru Koiwa ,  Nobuo Iwase

IPC分类号： H01L21/60

CPC分类号： H01L24/11 ,  H01L2224/1147 ,  H01L2224/13019 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082

摘要： A plating solution is stored in an annular plating solution storage. A plating solution tank having an open upper portion is arranged in a hollow portion of the storage. A mesh-like anode electrode is arranged on the bottom portion of the plating tank. Hold members are attached to an upper side wall of the plating tank. One of the hold members is in contact with a portion to be plated of a semiconductor member and serves as a cathode electrode. The anode and cathode electrodes are connected to a DC power source. The plating solution in the plating solution tank is brought into contact with the portion to be plated and is isolated therefrom by an driving pump intermittently driven at predetermined intervals using an intermittent drive unit. The power source is kept in the ON state while the plating solution is in contact with the portion to be plated, there-by forming a plated layer on the portion to be plated.