公开(公告)号：US20240339412A1

公开(公告)日：2024-10-10

申请号：US18130584

申请日：2023-04-04

Applicant: Intel Corporation

Inventor： Cary KULIASHA ,  Brandon C. MARIN ,  Kristof DARMAWIKARTA ,  Srinivas V. PIETAMBARAM

IPC: H01L23/538 ,  H01L23/64 ,  H01L25/065

CPC classification number: H01L23/5386 ,  H01L23/5384 ,  H01L23/645 ,  H01L25/0655 ,  H01L24/16 ,  H01L2224/16235 ,  H01L2924/1511

Abstract: Embodiments disclosed herein include an interconnect bridge. In an embodiment, the interconnect bridge comprises a substrate, and a first trace on the substrate. In an embodiment, a first layer is on the first trace, where the first layer comprises a magnetic material. In an embodiment, a second layer is over the substrate, where the second layer comprises an insulating material. In an embodiment, a second trace is embedded in the second layer.

公开(公告)号：US20240258240A1

公开(公告)日：2024-08-01

申请号：US18629424

申请日：2024-04-08

Applicant: Intel Corporation

Inventor： Robert Alan MAY ,  Wei-Lun Kane JEN ,  Jonathan L. ROSCH ,  Islam A. SALAMA ,  Kristof DARMAWIKARTA

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/683 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/5381 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/16227

Abstract: A device and method for providing enhanced bridge structures is disclosed. A set of conducting and insulating layers are deposited and lithographically processed. The conducting layers have uFLS routing. A bridge with uFLS contacts and die disposed on the underlying structure such that the die are connected with the uFLS contacts and uFLS routing. For core-based structures, the layers are formed after the bridge is placed on the underlying structure and the die connected to the bridge through intervening conductive layers. For coreless structures, the layers are formed over the bridge and carrier, which is removed prior to bonding the die to the bridge, and the die bonded directly to the bridge.

公开(公告)号：US20240217216A1

公开(公告)日：2024-07-04

申请号：US18091028

申请日：2022-12-29

Applicant: INTEL CORPORATION

Inventor： Kristof DARMAWIKARTA ,  Tarek A. IBRAHIM ,  Srinivas V. PIETAMBARAM ,  Dilan SENEVIRATNE ,  Jieying KONG ,  Thomas HEATON ,  Whitney BRYKS ,  Vinith BEJUGAM ,  Junxin WANG ,  Gang DUAN

IPC: B32B17/10 ,  B32B7/12 ,  B32B17/02 ,  B65D85/48

CPC classification number: B32B17/10642 ,  B32B7/12 ,  B32B17/02 ,  B65D85/48 ,  B32B2260/04 ,  B32B2307/202 ,  B32B2457/00

Abstract: Embodiments disclosed herein include package substrates with glass stiffeners. In an embodiment, the package substrate comprises a first layer, where the first layer comprises glass. In an embodiment, the package substrate comprises a second layer over the first layer, where the second layer is a buildup film. In an embodiment, the package substrate further comprises an electrically conductive interconnect structure through the first layer and the second layer.

公开(公告)号：US20240213301A1

公开(公告)日：2024-06-27

申请号：US18089471

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Darko GRUJICIC ,  Thomas L. SOUNART ,  Benjamin DUONG ,  Kristof DARMAWIKARTA ,  Shayan KAVIANI ,  Suddhasattwa NAD ,  Mahdi MOHAMMADIGHALENI ,  Marcel WALL ,  Rengarajan SHANMUGAM

IPC: H01G4/33

CPC classification number: H01L28/40 ,  H01G4/33

Abstract: Embodiments disclosed herein include a package core. In an embodiment, the package core comprises a core substrate that includes glass. In an embodiment, a cavity is provided into the core substrate. In an embodiment, a capacitor is lining sidewalls of the cavity, and the capacitor comprises a first layer, a dielectric layer over the first layer, and a second layer over the dielectric layer.

公开(公告)号：US20240213156A1

公开(公告)日：2024-06-27

申请号：US18089491

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Kristof DARMAWIKARTA ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Tarek A. IBRAHIM ,  Aaron GARELICK ,  Srikant NEKKANTY ,  Ravindranath V. MAHAJAN ,  Rahul N. MANEPALLI

IPC: H01L23/532 ,  H01L23/00 ,  H01L23/15 ,  H01L23/498 ,  H01L23/522 ,  H01L23/535 ,  H01L23/64 ,  H01L25/065

CPC classification number: H01L23/53209 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/5226 ,  H01L23/535 ,  H01L23/642 ,  H01L24/05 ,  H01L24/29 ,  H01L25/0655 ,  H01L2224/04026 ,  H01L2224/05567 ,  H01L2224/29007 ,  H01L2224/29021 ,  H01L2224/29101 ,  H01L2924/1436 ,  H01L2924/15321

Abstract: Embodiments disclosed herein include package substrates. In an embodiment, the package substrate comprises a core and buildup layers over the core. In an embodiment, a pad is provided on the buildup layers. In an embodiment, a liquid metal well is over the pad.

公开(公告)号：US20240213132A1

公开(公告)日：2024-06-27

申请号：US18089476

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Kristof DARMAWIKARTA ,  Benjamin DUONG ,  Darko GRUJICIC ,  Shayan KAVIANI ,  Mahdi MOHAMMADIGHALENI ,  Suddhasattwa NAD ,  Thomas L. SOUNART ,  Marcel WALL ,  Ravindranath V. MAHAJAN ,  Rahul N. MANEPALLI

IPC: H01L23/498 ,  H01L27/01

CPC classification number: H01L23/49838 ,  H01L27/016 ,  H01L28/86 ,  H01L28/90 ,  H01L23/49822 ,  H01L23/49894 ,  H01L24/16

Abstract: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate, where the package substrate comprises a plurality of stacked dielectric layers. In an embodiment, the electronic package further comprises an opening into the package substrate, where the opening passes through at least two of the plurality of dielectric layers. In an embodiment, a first pad is at the bottom of the opening, a capacitor is disposed in the opening, and a second pad is over the capacitor.

公开(公告)号：US20240178145A1

公开(公告)日：2024-05-30

申请号：US18434347

申请日：2024-02-06

Applicant: Intel Corporation

Inventor： Kristof DARMAWIKARTA ,  Hiroki TANAKA ,  Robert MAY ,  Sameer PAITAL ,  Bai NIE ,  Jesse JONES ,  Chung Kwang Christopher TAN

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L23/538 ,  H01L23/5226 ,  H01L23/5381 ,  H01L23/5385 ,  H01L24/82 ,  H01L2224/12105

Abstract: Embodiments include an electronic package with an embedded multi-interconnect bridge (EMIB) and methods of making such packages. Embodiments include a first layer, that is an organic material and a second layer disposed over the first layer. In an embodiment, a cavity is formed through the second layer to expose a first surface of the first layer. A bridge substrate is in the cavity and is supported by the first surface of the first layer. Embodiments include a first die over the second layer that is electrically coupled to a first contact on the bridge substrate, and a second die over the second layer that is electrically coupled to a second contact on the bridge substrate. In an embodiment the first die is electrically coupled to the second die by the bridge substrate.

公开(公告)号：US20240105621A1

公开(公告)日：2024-03-28

申请号：US18525435

申请日：2023-11-30

Applicant: Intel Corporation

Inventor： Robert Alan MAY ,  Kristof DARMAWIKARTA ,  Sri Ranga Sai Sai BOYAPATI

IPC: H01L23/532 ,  H01L23/29 ,  H01L23/522

CPC classification number: H01L23/5329 ,  H01L23/293 ,  H01L23/5226 ,  H01L23/5385

Abstract: A die interconnect substrate comprises a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate comprises a multilayer substrate structure comprising a substrate interconnect. The bridge die is embedded in the multilayer substrate structure. The substrate interconnect extends from a level above the bridge die to a level below the bridge die. The multilayer substrate structure further comprises an electrically insulating layer comprising a first electrically insulating material. The multilayer substrate structure further comprises an electrically insulating filler structure located laterally between the bridge die and the electrically insulating layer, wherein the electrically insulating filler structure comprises a second electrically insulating material different from the first electrically insulating material.

公开(公告)号：US20240088121A1

公开(公告)日：2024-03-14

申请号：US18511641

申请日：2023-11-16

Applicant: Intel Corporation

Inventor： Srinivas PIETAMBARAM ,  Robert Alan MAY ,  Kristof DARMAWIKARTA ,  Hiroki TANAKA ,  Rahul N. MANEPALLI ,  Sri Ranga Sai BOYAPATI

IPC: H01L25/00 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49866 ,  H01L23/5385 ,  H01L23/5389 ,  H01L25/0652 ,  H01L24/14

Abstract: Techniques for a patch to couple one or more surface dies to an interposer or motherboard are provided. In an example, the patch can include multiple embedded dies. In an example, a microelectronic device can be formed to include a patch on an interposer, where the patch can include multiple embedded dies and each die can have a different thickness.

公开(公告)号：US20240006297A1

公开(公告)日：2024-01-04

申请号：US17853582

申请日：2022-06-29

Applicant: Intel Corporation

Inventor： Suddhasattwa NAD ,  Kristof DARMAWIKARTA ,  Srinivas V. PIETAMBARAM ,  Tarek A. IBRAHIM ,  Rahul N. MANEPALLI ,  Darko GRUJICIC ,  Marcel WALL ,  Yi YANG

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01L23/49894 ,  H01L21/4846 ,  H01L23/538 ,  H01L21/481

Abstract: Embodiments herein relate to systems, apparatuses, or processes for forming a silicide and a silicon nitrate layer between a copper feature and dielectric to reduce delamination of the dielectric. Embodiments allow an unroughened surface for the copper feature to reduce the insertion loss for transmission lines that go through the unroughened surface of the copper. Embodiments may include sequential interlayers between a dielectric and copper. Other embodiments may be described and/or claimed.