中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

112 records (took 0.021 seconds)

    Low cost package warpage solution
    54.
    发明授权
    Low cost package warpage solution 有权

    公开(公告)号：US10741419B2

    公开(公告)日：2020-08-11

    申请号：US16515981

    申请日：2019-07-18

    Applicant: Intel Corporation

    Inventor： Omkar G. Karhade ,  Nitin A. Deshpande ,  Debendra Mallik ,  Bassam M. Ziadeh ,  Yoshihiro Tomita

    IPC: H01L23/00 ,  H01L21/56 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/16

    Abstract: Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.

    MOLD MATERIAL ARCHITECTURE FOR PACKAGE DEVICE STRUCTURES
    55.
    发明申请
    MOLD MATERIAL ARCHITECTURE FOR PACKAGE DEVICE STRUCTURES 审中-公开

    公开(公告)号：US20190330051A1

    公开(公告)日：2019-10-31

    申请号：US15962912

    申请日：2018-04-25

    Applicant: Intel Corporation

    Inventor： Omkar G. Karhade ,  Nitin A. Deshpande

    IPC: B81B7/00 ,  B81C1/00

    Abstract: Embodiments include a microelectronic device package structure having a die on a substrate, where a first side of the die is electrically coupled to the substrate, and a second side of the die is covered with a first material having a first thermal conductivity. A second material is adjacent to a sidewall of the die and adjacent to a sidewall of the first material. The second material has second thermal conductivity, smaller than the first thermal conductivity. The second material may have mechanical and/or underfill properties superior to those of the first material. Together, the two materials may provide a package structure having enhanced thermal and mechanical performance.

    Thermal interfaces for integrated circuit packages
    56.
    发明授权
    Thermal interfaces for integrated circuit packages 有权

    公开(公告)号：US10290561B2

    公开(公告)日：2019-05-14

    申请号：US15279222

    申请日：2016-09-28

    Applicant: Intel Corporation

    Inventor： Edvin Cetegen ,  Omkar G. Karhade ,  Kedar Dhane ,  Chandra M. Jha

    IPC: H01L23/367 ,  H01L23/373 ,  H01L23/42 ,  H01L23/427 ,  H01L23/433

    Abstract: A thermal interface may include a wired network made of a first TIM, and a second TIM surrounding the wired network. A heat spreader lid may include a wired network attached to an inner surface of the heat spreader lid. An IC package may include a heat spreader lid placed over a first electronic component and a second electronic component. A first thermal interface may be formed between the first electronic component and the inner surface of the heat spreader lid, and a second thermal interface may be formed between the second electronic component and the inner surface of the heat spreader lid. The first thermal interface may include a wired network of a first TIM surrounded by a second TIM, while the second thermal interface may include the second TIM, without a wired network of the first TIM. Other embodiments may be described and/or claimed.

    High bandwidth, low profile multi-die package
    57.
    发明授权
    High bandwidth, low profile multi-die package 有权

    公开(公告)号：US10109616B2

    公开(公告)日：2018-10-23

    申请号：US15388606

    申请日：2016-12-22

    Applicant: Intel Corporation

    Inventor： Omkar G. Karhade

    IPC: H01L23/34 ,  H01L25/10 ,  H01L23/31 ,  H01L23/538 ,  H01L23/473 ,  H01L23/367 ,  H01L25/00 ,  H01L21/56

    Abstract: An embodiment includes an apparatus comprising: a substrate; a first die including a processor core; a second die not including a processor core; and a third die including memory cells; wherein: (a)(i) the first die has a smaller minimum pitch than the second die; (a)(ii) a first vertical axis intersects the substrate and the first and second dies but not the third die; and (a)(iii) a second vertical axis intersects the substrate and the second and third dies but not the first die. Other embodiments are described herein.

Patent Agency Ranking