公开(公告)号：US20150028419A1

公开(公告)日：2015-01-29

申请号：US13952993

申请日：2013-07-29

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Ramachandra Divakaruni ,  Ali Khakifirooz ,  Kern Rim

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L21/845 ,  H01L27/1211 ,  H01L29/7848

Abstract: A first fin field effect transistor and a second fin field effect transistor are formed on an insulator layer overlying a semiconductor material layer. A first pair of trenches is formed through the insulator layer in regions in which a source region and a drain region of the first fin field effect transistor is to be formed. A second pair of trenches is formed partly into the insulator layer without extending to the top surface of the semiconductor material layer. The source region and the drain region of the first field effect transistor can be epitaxial stressor material portions that are anchored to, and epitaxially aligned to, the semiconductor material layer and apply stress to the channel of the first field effect transistor to enhance performance. The insulator layer provides electrical isolation from the semiconductor material layer to the second field effect transistor.

Abstract translation: 第一鳍状场效应晶体管和第二鳍状场效应晶体管形成在覆盖半导体材料层的绝缘体层上。 在要形成第一鳍式场效应晶体管的源极区域和漏极区域的区域中，通过绝缘体层形成第一对沟槽。 第二对沟槽部分地形成绝缘体层，而不延伸到半导体材料层的顶表面。 第一场效应晶体管的源极区域和漏极区域可以是外延应力材料部分，其被锚定并外延对准半导体材料层，并且将应力施加到第一场效应晶体管的沟道以增强性能。 绝缘体层提供从半导体材料层到第二场效应晶体管的电隔离。

公开(公告)号：US20150028398A1

公开(公告)日：2015-01-29

申请号：US13953024

申请日：2013-07-29

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Ramachandra Divakaruni ,  Bruce B. Doris ,  Ali Khakifirooz ,  Edward J. Nowak ,  Kern Rim

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/785

Abstract: An array of stacks containing a semiconductor fins and an oxygen-impermeable cap is formed on a semiconductor substrate with a substantially uniform areal density. Oxygen-impermeable spacers are formed around each stack, and the semiconductor substrate is etched to vertically extend trenches. Semiconductor sidewalls are physically exposed from underneath the oxygen-impermeable spacers. The oxygen-impermeable spacers are removed in regions in which semiconductor fins are not needed. A dielectric oxide material is deposited to fill the trenches. Oxidation is performed to convert a top portion of the semiconductor substrate and semiconductor fins not protected by oxygen-impermeable spacers into dielectric material portions. Upon removal of the oxygen-impermeable caps and remaining oxygen-impermeable spacers, an array including semiconductor fins and dielectric fins is provided. The dielectric fins alleviate variations in the local density of protruding structures, thereby reducing topographical variations in the height of gate level structures to be subsequently formed.

Abstract translation: 在半导体衬底上形成具有基本均匀的面密度的包含半导体鳍片和不透氧帽的叠层阵列。 在每个堆叠周围形成不透氧的间隔物，并且蚀刻半导体衬底以垂直延伸沟槽。 半导体侧壁从不透氧间隔物的下方物理暴露。 在不需要半导体散热片的区域中去除不透氧隔离物。 沉积电介质氧化物材料以填充沟槽。 执行氧化以将半导体衬底的顶部部分和不被不透氧隔离物保护的半导体鳍片转换成电介质材料部分。 在除去不透氧的盖子和剩余的不透氧隔离物之后，提供了包括半导体鳍片和介电鳍片的阵列。 介电散热片减轻突出结构的局部密度的变化，从而减少随后形成的栅极层结构的高度的形貌变化。

公开(公告)号：US20140266254A1

公开(公告)日：2014-09-18

申请号：US14029585

申请日：2013-09-17

Applicant: International Business Machines Corporation

Inventor： Wilfried E.A. Haensch ,  Chung-Hsun Lin ,  Philip J. Oldiges ,  Kern Rim

IPC: G01B7/06

CPC classification number: H01L22/12 ,  G01B7/08 ,  G01B2210/56 ,  H01L22/14 ,  H01L22/34 ,  H01L27/0886

Abstract: Techniques for quantifying ΔDfin in FINFET technology are provided. In one aspect, a method for quantifying ΔDfin between a pair of long channel FINFET devices includes the steps of: (a) obtaining Vth values for each of the long channel FINFET devices in the pair; (b) determining a ΔVth for the pair of long channel FINFET devices; and (c) using the ΔVth to determine the ΔDfin between the pair of long channel FINFET devices, wherein the ΔVth is a function of a difference in a Qbody and a gate capacitance between the pair of long channel FINFET devices, and wherein the Qbody is a function of Dfin and Nch for each of the long channel FINFET devices in the pair, and as such the ΔVth is proportional to the ΔDfin between the pair of long channel FINFET devices.

公开(公告)号：US08766363B2

公开(公告)日：2014-07-01

申请号：US13670768

申请日：2012-11-07

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Veeraraghavan S. Basker ,  Bruce B. Doris ,  Ali Khakifirooz ,  Kern Rim

IPC: H01L27/12

CPC classification number: H01L27/1211 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/785

Abstract: Methods and structures for forming a localized silicon-on-insulator (SOI) finFET are disclosed. Fins are formed on a bulk substrate. Nitride spacers protect the fin sidewalls. A shallow trench isolation region is deposited over the fins. An oxidation process causes oxygen to diffuse through the shallow trench isolation region and into the underlying silicon. The oxygen reacts with the silicon to form oxide, which provides electrical isolation for the fins. The shallow trench isolation region is in direct physical contact with the fins and/or the nitride spacers that are disposed on the fins.

Abstract translation: 公开了用于形成局部绝缘体上硅（SOI）finFET的方法和结构。 翅片形成在块状基底上。 氮化物间隔件保护翅片侧壁。 浅沟槽隔离区域沉积在鳍片上。 氧化过程导致氧气扩散通过浅沟槽隔离区域并进入下面的硅。 氧与硅反应形成氧化物，为散热片提供电气隔离。 浅沟槽隔离区域与布置在鳍片上的翅片和/或氮化物间隔物直接物理接触。

公开(公告)号：US20140123097A1

公开(公告)日：2014-05-01

申请号：US14148234

申请日：2014-01-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Paul Chang ,  Jie Deng ,  Terrence B. Hook ,  Sim Y. Loo ,  Anda C. Mocuta ,  Jeae-Eun Park ,  Kern Rim ,  Xiaojun Yu

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G01R31/2848 ,  G01R31/3008 ,  G06F17/5009 ,  G06F17/5022 ,  G06F17/5036

Abstract: A system, method and computer program product for implementing a quiescent current leakage specific model into semiconductor device design and circuit design flows. The leakage model covers all device geometries with wide temperature and voltage ranges and, without the need for stacking factor calculations nor spread sheet based IDDQ calculations. The leakage model for IDDQ calculation incorporates further parasitic and proximity effects. The leakage model implements leakage calculations at different levels of testing, e.g., from a single device to a full chip design, and are integrated within one single model. The leakage model implements leakage calculations at different levels of testing with the leverage of a single switch setting. The implementation is via a hardware definition language code or object oriented code that can be compiled and operated using a netlist of interest, e.g., for conducting a performance analysis.

Abstract translation: 一种用于将静态电流泄漏特定模型实现为半导体器件设计和电路设计流程的系统，方法和计算机程序产品。 泄漏模型涵盖宽温度和电压范围的所有器件几何，并且不需要堆叠因子计算，也不需要基于平板的IDDQ计算。 IDDQ计算的泄漏模型包含进一步的寄生和邻近效应。 泄漏模型在不同的测试水平下实施泄漏计算，例如从单个设备到全芯片设计，并且集成在一个单一的模型中。 泄漏模型通过单个开关设置的杠杆来实现不同测试级别的泄漏计算。 该实现是通过硬件定义语言代码或面向对象的代码，其可以使用感兴趣的网表来编译和操作，例如用于进行性能分析。

公开(公告)号：US11728428B2

公开(公告)日：2023-08-15

申请号：US16682645

申请日：2019-11-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Darsen D. Lu ,  Ali Khakifirooz ,  Kern Rim

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/311 ,  H01L21/308 ,  H01L21/306 ,  H01L21/324 ,  H01L29/10 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L29/7846 ,  H01L21/02236 ,  H01L21/3086 ,  H01L21/30604 ,  H01L21/311 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/324 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a fin structure that includes forming a plurality of fin structures from a bulk semiconductor substrate and forming a dielectric spacer on a sidewall of each fin structure in the plurality of fin structure. A semiconductor spacer is formed on a sidewall of the dielectric spacer. A dielectric fill is formed in the space between the adjacent fin structures. The semiconductor spacer and a portion of the fin structures that is present below a lower surface of the dielectric spacer are oxidized. Oxidizing a base portion of the fin structures produces a first strain and oxidizing the semiconductor spacer produces a second strain that is opposite the first strain.

公开(公告)号：US10892364B2

公开(公告)日：2021-01-12

申请号：US15800740

申请日：2017-11-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Darsen D. Lu ,  Ali Khakifirooz ,  Kern Rim

IPC: H01L29/772 ,  H01L29/78 ,  H01L29/66 ,  H01L21/311 ,  H01L21/308 ,  H01L21/306 ,  H01L21/324 ,  H01L29/10 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/762 ,  H01L29/06

Abstract: A method of forming a fin structure that includes forming a plurality of fin structures from a bulk semiconductor substrate and forming a dielectric spacer on a sidewall of each fin structure in the plurality of fin structure. A semiconductor spacer is formed on a sidewall of the dielectric spacer. A dielectric fill is formed in the space between the adjacent fin structures. The semiconductor spacer and a portion of the fin structures that is present below a lower surface of the dielectric spacer are oxidized. Oxidizing a base portion of the fin structures produces a first strain and oxidizing the semiconductor spacer produces a second strain that is opposite the first strain.

公开(公告)号：US10886385B2

公开(公告)日：2021-01-05

申请号：US16375890

申请日：2019-04-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Darsen D. Lu ,  Alexander Reznicek ,  Kern Rim

IPC: H01L27/092 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/165 ,  H01L21/84 ,  H01L29/78 ,  H01L21/02 ,  H01L21/033 ,  H01L21/32 ,  H01L21/324 ,  H01L29/10 ,  H01L29/161

Abstract: A method of introducing strain in a channel region of a FinFET device includes forming a fin structure on a substrate, the fin structure having a lower portion comprising a sacrificial layer and an upper portion comprising a strained semiconductor layer; and removing a portion of the sacrificial layer corresponding to a channel region of the FinFET device so as to release the upper portion of the fin structure from the substrate in the channel region.

公开(公告)号：US09997540B2

公开(公告)日：2018-06-12

申请号：US15407992

申请日：2017-01-17

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Darsen D. Lu ,  Alexander Reznicek ,  Kern Rim

IPC: H01L27/12 ,  H01L29/78 ,  H01L27/092 ,  H01L29/10 ,  H01L29/165 ,  H01L29/66 ,  H01L21/84 ,  H01L21/02 ,  H01L21/308 ,  H01L21/311 ,  H01L21/32 ,  H01L21/324

CPC classification number: H01L27/1211 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/18 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/31116 ,  H01L21/32 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7845 ,  H01L29/785

Abstract: A method of forming a semiconductor structure that includes a tensily strained silicon fin extending upwards from a first portion of a substrate and in an nFET device region, and a SiGe fin structure extending upwards from a second portion of the substrate and in a pFET device region. In accordance with the present application, the SiGe fin structure comprises, from bottom to top, a lower SiGe fin that is relaxed and an upper SiGe fin, wherein the upper SiGe fin is compressively strained and has a germanium content that is greater than a germanium content of the lower SiGe fin.

公开(公告)号：US09911597B2

公开(公告)日：2018-03-06

申请号：US15595503

申请日：2017-05-15

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Michael P. Chudzik ,  Aritra Dasgupta ,  Herbert L. Ho ,  Donghun Kang ,  Rishikesh Krishnan ,  Vijay Narayanan ,  Kern Rim

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/322 ,  H01L21/20 ,  H01G4/005 ,  H01L27/108 ,  H01L49/02

CPC classification number: H01L21/02365 ,  H01G4/005 ,  H01L21/02178 ,  H01L21/02617 ,  H01L21/20 ,  H01L21/3221 ,  H01L23/26 ,  H01L27/10861 ,  H01L27/1087 ,  H01L28/60 ,  H01L28/90 ,  H01L29/66181 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method including forming an oxygen gettering layer on one side of an insulating layer of a deep trench capacitor between the insulating layer and a substrate, the oxygen gettering layer including an aluminum containing compound, and depositing an inner electrode on top of the insulating layer, the inner electrode including a metal.