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    Chip structure to improve resistance-capacitance delay and reduce energy loss of the chip
    55.
    发明授权
    Chip structure to improve resistance-capacitance delay and reduce energy loss of the chip 有权
    芯片结构提高电阻电容延迟并减少芯片的能量损耗

    公开(公告)号：US06700162B2

    公开(公告)日：2004-03-02

    申请号：US10337673

    申请日：2003-01-06

    申请人： Mou-Shiung Lin ,  Jin-Yuan Lee ,  Ching-Cheng Huang

    发明人： Mou-Shiung Lin ,  Jin-Yuan Lee ,  Ching-Cheng Huang

    IPC分类号： H01L2348

    CPC分类号： H01L21/768 ,  H01L21/76807 ,  H01L21/76838 ,  H01L23/522 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/5329 ,  H01L23/60 ,  H01L24/05 ,  H01L24/13 ,  H01L24/45 ,  H01L27/0676 ,  H01L27/08 ,  H01L28/10 ,  H01L28/20 ,  H01L2221/1036 ,  H01L2224/0401 ,  H01L2224/16 ,  H01L2224/45 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/15174 ,  H01L2924/19041 ,  H01L2924/19051 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2224/48 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

    摘要： A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer. The second built-up layer is provided with a second dielectric body and a second interconnection scheme, wherein the second interconnection scheme interlaces inside the second dielectric body and is electrically connected to the first interconnection scheme. The second interconnection scheme is constructed from at least one second metal layer and at least one via metal filler, wherein the second metal layer is electrically connected to the via metal filler. The thickness, width, and cross-sectional area of the traces of the second metal layer are respectively larger than those of the first metal layers.

    摘要翻译： 芯片结构包括基板，第一堆叠层，钝化层和第二堆积层。 基板包括放置在基板的表面上的许多电气装置。 第一组合层位于基底上。 第一组合层设置有第一电介质体和第一互连方案，其中第一互连方案与第一介电体内部交错并电连接到电气装置。 第一互连方案由第一金属层和插塞构成，其中相邻的第一金属层通过插塞电连接。 钝化层设置在第一堆叠层上并且设有暴露第一互连方案的开口。 第二堆叠层形成在钝化层上。 第二组合层设置有第二电介质体和第二互连方案，其中第二互连方案在第二介电体内部交织并与第一互连方案电连接。 第二互连方案由至少一个第二金属层和至少一个通孔金属填料构成，其中第二金属层电连接到通孔金属填料。 第二金属层的迹线的厚度，宽度和横截面积分别大于第一金属层的厚度，宽度和横截面面积。