公开(公告)号：US20150296616A1

公开(公告)日：2015-10-15

申请号：US14251486

申请日：2014-04-11

Applicant: QUALCOMM Incorporated

Inventor： Houssam Wafic Jomaa ,  Omar James Bchir ,  Chin-Kwan Kim

IPC: H05K1/11 ,  H05K3/42 ,  H05K1/02

CPC classification number: H05K1/112 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K1/0298 ,  H05K3/422 ,  H05K3/425 ,  H05K3/429 ,  H05K2201/0344 ,  H05K2201/09036 ,  H05K2201/10378

Abstract: Some novel features pertain to a substrate that includes a first dielectric layer, a first interconnect, a first cavity, and a first electroless metal layer. The first dielectric layer includes a first surface and a second surface. The first interconnect is on the first surface of the substrate layer. The first cavity traverses the first surface of the first dielectric layer. The first electroless metal layer is formed at least partially in the first cavity. The first electroless metal layer defines a second interconnect embedded in the first dielectric layer. In some implementations, the substrate further includes a core layer. The core layer includes a first surface and a second surface. The first surface of the core layer is coupled to the second surface of the first dielectric layer. In some implementations, the substrate further includes a second dielectric layer.

Abstract translation: 一些新颖特征涉及包括第一介电层，第一互连，第一空腔和第一无电金属层的基板。 第一电介质层包括第一表面和第二表面。 第一互连在衬底层的第一表面上。 第一空腔穿过第一介电层的第一表面。 第一无电金属层至少部分地形成在第一腔中。 第一无电金属层限定嵌入在第一介电层中的第二互连。 在一些实施方案中，衬底还包括芯层。 芯层包括第一表面和第二表面。 芯层的第一表面耦合到第一介电层的第二表面。 在一些实施方案中，衬底还包括第二介电层。

公开(公告)号：US20150294933A1

公开(公告)日：2015-10-15

申请号：US14253798

申请日：2014-04-15

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Chin-Kwan Kim ,  Dong Wook Kim ,  Jae Sik Lee ,  Kyu-Pyung Hwang ,  Young Kyu Song

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L21/768 ,  H01L21/4857 ,  H01L21/76802 ,  H01L21/76838 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/49822 ,  H01L23/5283 ,  H01L23/5329 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/014

Abstract: An integrated circuit (IC) substrate that includes a second patterned metal layer formed in between a first patterned metal layer is disclosed. A dielectric layer formed on the first patterned metal layer separates the two metal layers. A non-conductive layer is formed on the dielectric layer and the second patterned metal layer.

Abstract translation: 公开了一种集成电路（IC）基板，其包括形成在第一图案化金属层之间的第二图案化金属层。 形成在第一图案化金属层上的电介质层分离两个金属层。 在介电层和第二图案化金属层上形成非导电层。

公开(公告)号：US09155191B2

公开(公告)日：2015-10-06

申请号：US13967186

申请日：2013-08-14

Applicant: QUALCOMM Incorporated

Inventor： Chin-Kwan Kim

IPC: B32B9/00 ,  H05K1/02 ,  H05K3/46 ,  H01L23/31 ,  H05K1/03

CPC classification number: H05K1/0271 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/562 ,  H01L2224/131 ,  H01L2224/16165 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/16251 ,  H01L2924/3511 ,  H05K1/0306 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/068 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10734 ,  Y10T428/31678 ,  H01L2924/014

Abstract: Some novel features pertain to a substrate that includes a first core layer, a second core layer laterally located to the first core layer in the substrate, a first inorganic core layer (e.g., glass, silicon, ceramic) laterally positioned between the first core layer and the second core layer, the first inorganic core layer configured to be vertically aligned with a die configured to be coupled to the substrate, and a dielectric layer covering the first core layer, the second core layer and the first inorganic core layer. In some implementations, the first inorganic core layer has a first coefficient of thermal expansion (CTE), the die has a second coefficient of thermal expansion, and the first core layer has a third coefficient of thermal expansion (CTE). The first CTE of the first inorganic core layer closely matches the second CTE of the die in order to reduce the likelihood of warpage.

Abstract translation: 一些新颖特征涉及一种衬底，其包括第一芯层，横向位于衬底中的第一芯层的第二芯层，侧向位于第一芯层之间的第一无机芯层（例如，玻璃，硅，陶瓷） 和第二芯层，被配置为与被配置为耦合到基板的管芯垂直对准的第一无机芯层，以及覆盖第一芯层，第二芯层和第一无机芯层的电介质层。 在一些实施方案中，第一无机核心层具有第一热膨胀系数（CTE），所述管芯具有第二热膨胀系数，并且所述第一核心层具有第三热膨胀系数（CTE）。 第一无机芯层的第一CTE与模具的第二CTE紧密匹配，以减少翘曲的可能性。

公开(公告)号：US20150061143A1

公开(公告)日：2015-03-05

申请号：US14318490

申请日：2014-06-27

Applicant: QUALCOMM Incorporated

Inventor： Chin-Kwan Kim ,  Rajneesh Kumar ,  Omar James Bchir

IPC: H01L23/528 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/768 ,  H01L23/498 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/131 ,  H01L2224/14133 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/17051 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2924/3841 ,  H05K1/0296 ,  H05K1/111 ,  H05K3/4682 ,  H05K2201/0376 ,  H05K2201/094 ,  Y02P70/611 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Some novel features pertain to a substrate that includes a first dielectric layer, a first interconnect, a first cavity, and a second interconnect. The first dielectric layer includes first and second surfaces. The first interconnect is embedded in the first dielectric layer. The first interconnect includes a first side and a second side. The first side is surrounded by the first dielectric layer, where at least a part of the second side is free of contact with the first dielectric layer. The first cavity traverses the first surface of the first dielectric layer to the second side of the first interconnect, where the first cavity overlaps the first interconnect. The second interconnect includes a third side and a fourth side, where the third side is coupled to the first surface of the first dielectric layer.

Abstract translation: 一些新颖的特征涉及包括第一介电层，第一互连，第一腔和第二互连的衬底。 第一介电层包括第一和第二表面。 第一互连嵌入在第一电介质层中。 第一互连包括第一侧和第二侧。 第一侧被第一介电层包围，其中第二侧的至少一部分与第一介电层不接触。 第一空腔穿过第一介电层的第一表面到第一互连的第二侧，其中第一腔与第一互连重叠。 第二互连包括第三侧和第四侧，其中第三侧耦合到第一介电层的第一表面。

公开(公告)号：US20140264946A1

公开(公告)日：2014-09-18

申请号：US13833921

申请日：2013-03-15

Applicant: QUALCOMM Incorporated

Inventor： Chin-Kwan Kim ,  Omar James Bchir ,  Milind Pravin Shah ,  Marcus Bernard Hsu ,  David Fraser Rae

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/563 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/82 ,  H01L25/03 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18165 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: To achieve a package-on-package having an advantageously reduced height, a first package substrate has a window sized to receive a second package die. The first package substrate interconnects to the second package substrate through a plurality of package-to-package interconnects such that the first and second substrates are separated by a gap. The second package die has a thickness greater than the gap such that the second package die is at least partially disposed within the first package substrate's window.

Abstract translation: 为了实现具有有利地降低的高度的封装封装，第一封装衬底具有尺寸适于接收第二封装管芯的窗口。 第一封装衬底通过多个封装到封装互连而互连到第二封装衬底，使得第一和第二衬底被间隙隔开。 第二封装管芯具有大于间隙的厚度，使得第二封装管芯至少部分地设置在第一封装衬底的窗口内。

公开(公告)号：US20140175658A1

公开(公告)日：2014-06-26

申请号：US13764959

申请日：2013-02-12

Applicant: QUALCOMM INCORPORATED

Inventor： Chin-Kwan Kim ,  Houssam W. Jomaa ,  Milind P. Shah ,  Manuel Aldrete ,  Omar J. Bchir

IPC: H01L21/50 ,  H01L23/48

CPC classification number: H01L23/48 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/13564 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81385 ,  H01L2924/07802 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: Sonic implementations pertain to a semiconductor device that includes a packaging substrate, a trace coupled to the packaging substrate, and a solder resist layer that covers part of the trace. The trace includes a first portion having a first width, and a second portion having a second width that is wider than the first width. In some implementations, the second portion having the second width increases the area of the trace coupled to the packaging substrate to reduce the likelihood of the trace peeling from the packaging substrate. In some implementations, the solder resist layer further includes an opening such that the second portion of the trace is exposed. In some implementations, the trace further includes a third portion located between the first portion and second portion of the trace and wherein the third portion of the trace is exposed through an opening in the solder resist layer.

Abstract translation: 声波实现涉及包括封装衬底，耦合到封装衬底的迹线和覆盖部分迹线的阻焊层的半导体器件。 迹线包括具有第一宽度的第一部分和具有宽于第一宽度的第二宽度的第二部分。 在一些实施方案中，具有第二宽度的第二部分增加了耦合到包装衬底的迹线的面积，以减少从包装衬底的迹线剥离的可能性。 在一些实施方案中，阻焊层还包括开口，使得迹线的第二部分被暴露。 在一些实施方案中，迹线还包括位于迹线的第一部分和第二部分之间的第三部分，并且其中迹线的第三部分通过阻焊层中的开口露出。