公开(公告)号：US20170243899A1

公开(公告)日：2017-08-24

申请号：US15591145

申请日：2017-05-10

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hidekazu MIYAIRI ,  Yuichi SATO ,  Yuji ASANO ,  Tetsunori MARUYAMA ,  Tatsuya ONUKI ,  Shuhei NAGATSUKA

IPC: H01L27/12 ,  H01L23/485 ,  H01L23/522 ,  H01L21/8258 ,  H01L27/06 ,  H01L29/786 ,  H01L21/768 ,  H01L23/48 ,  H01L23/532

CPC classification number: H01L27/1225 ,  H01L21/76807 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76885 ,  H01L21/8258 ,  H01L23/481 ,  H01L23/485 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53295 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/1207 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/16 ,  H01L29/45 ,  H01L29/78 ,  H01L29/78603 ,  H01L29/7869 ,  H01L29/78696

Abstract: To provide a semiconductor device with excellent electrical characteristics or a semiconductor device with stable electrical characteristics. A semiconductor device includes a first transistor, a second transistor, a first insulator, a second insulator, a first wiring, and a first plug. The first transistor includes silicon. The second transistor includes an oxide semiconductor. The first insulator is located over the first transistor. The second insulator is located over the first insulator. The second transistor is located over the second insulator. The first wiring is located over the second insulator and the first plug. The first transistor and the second transistor are electrically connected to each other through the first wiring and the first plug. The first wiring has low hydrogen permeability. The hydrogen permeability of the second insulator is lower than the hydrogen permeability of the first insulator.

公开(公告)号：US20170178752A1

公开(公告)日：2017-06-22

申请号：US15391929

申请日：2016-12-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tomoaki ATSUMI ,  Shuhei NAGATSUKA ,  Kazuaki OHSHIMA

IPC: G11C29/50 ,  H01L27/108 ,  G11C11/4096

CPC classification number: G11C29/50004 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/401 ,  G11C11/4096 ,  G11C29/50016 ,  H01L27/108

Abstract: The semiconductor device includes a bit line, a transistor, a retention node, and a capacitor. The transistor has a function of charging or discharging the retention node. The capacitor has a function of retaining a potential of the retention node. A voltage greater than the sum of a writing voltage and a threshold voltage is applied to a gate of the transistor. When the transistor is turned on, a first potential is supplied to the bit line with a reference potential in a floating state. A voltage less than the sum of the writing voltage and the threshold voltage is applied to the gate of the transistor. When the transistor is turned on, a second potential is supplied to the bit line with a reference potential in a floating state. With use of the first and second potentials, the threshold voltage of the transistor is calculated without being influenced by parasitic capacitance and variations in the storage capacitance of the capacitor.

公开(公告)号：US20170178699A1

公开(公告)日：2017-06-22

申请号：US15447809

申请日：2017-03-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takahiko ISHIZU ,  Shuhei NAGATSUKA

IPC: G11C7/06 ,  H01L27/105 ,  G11C7/18 ,  G11C8/14 ,  G11C5/06 ,  G11C7/12

CPC classification number: G11C7/065 ,  G11C5/025 ,  G11C5/06 ,  G11C5/063 ,  G11C7/06 ,  G11C7/12 ,  G11C7/18 ,  G11C8/14 ,  G11C8/16 ,  G11C11/403 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2207/002 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/1052 ,  H01L27/1108 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1251 ,  H01L27/1255 ,  H01L29/7869 ,  H01L29/78696

Abstract: A column driver includes an amplifier circuit for amplifying data of a read bit line and a latch circuit for retaining the amplified data. The latch circuit includes a pair of nodes Q and QB for retaining complementary data. Data is read from a memory cell in each write target row to a read bit line, and amplified by the amplifier circuit. The amplified data is written to the node Q (or QB) of the latch circuit. In a write target column, write data is input to the latch circuit through the node Q (or QB) to update data of the latch circuit. Then, in each column, data of the latch circuit is written to a write bit line, and the data of the write bit line is written to the memory cell.

公开(公告)号：US20170062482A1

公开(公告)日：2017-03-02

申请号：US15245310

申请日：2016-08-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Kiyoshi KATO ,  Yuto YAKUBO ,  Shuhei NAGATSUKA

IPC: H01L27/12 ,  H01L23/544 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/1225 ,  H01L23/544 ,  H01L27/1207 ,  H01L27/1259 ,  H01L29/66969 ,  H01L29/7869 ,  H01L2223/54453

Abstract: To provide a semiconductor device that is not easily damaged by ESD in a manufacturing process thereof. A layer whose band gap is greater than or equal to 2.5 eV and less than or equal to 4.2 eV, preferably greater than or equal to 2.7 eV and less than or equal to 3.5 eV is provided to overlap with a dicing line. A layer whose band gap is greater than or equal to 2.5 eV and less than or equal to 4.2 eV, preferably greater than or equal to 2.7 eV and less than or equal to 3.5 eV is provided around the semiconductor device such as a transistor. The layer may be in a floating state or may be supplied with a specific potential.

Abstract translation: 提供在其制造过程中不容易被ESD损坏的半导体器件。 带隙大于或等于2.5eV且小于或等于4.2eV，优选大于或等于2.7eV且小于或等于3.5eV的层被提供以与切割线重叠。 在诸如晶体管的半导体器件周围设置一个其带隙大于或等于2.5eV且小于或等于4.2eV，优选大于或等于2.7eV且小于或等于3.5eV的层。 该层可以处于浮置状态或者可以被提供特定的电位。

公开(公告)号：US20160276370A1

公开(公告)日：2016-09-22

申请号：US15072076

申请日：2016-03-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hidekazu MIYAIRI ,  Yuichi SATO ,  Yuji ASANO ,  Tetsunori MARUYAMA ,  Tatsuya ONUKI ,  Shuhei NAGATSUKA

IPC: H01L27/12 ,  H01L23/528 ,  H01L29/16 ,  H01L23/532 ,  H01L29/78 ,  H01L29/786 ,  H01L23/522

CPC classification number: H01L27/1225 ,  H01L21/76807 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76885 ,  H01L21/8258 ,  H01L23/481 ,  H01L23/485 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53295 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/1207 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/16 ,  H01L29/45 ,  H01L29/78 ,  H01L29/78603 ,  H01L29/7869 ,  H01L29/78696

Abstract: To provide a semiconductor device with excellent electrical characteristics or a semiconductor device with stable electrical characteristics. A semiconductor device includes a first transistor, a second transistor, a first insulator, a second insulator, a first wiring, and a first plug. The first transistor includes silicon. The second transistor includes an oxide semiconductor. The first insulator is located over the first transistor. The second insulator is located over the first insulator. The second transistor is located over the second insulator. The first wiring is located over the second insulator and the first plug. The first transistor and the second transistor are electrically connected to each other through the first wiring and the first plug. The first wiring has low hydrogen permeability. The hydrogen permeability of the second insulator is lower than the hydrogen permeability of the first insulator.

Abstract translation: 提供具有优异电气特性的半导体器件或具有稳定电特性的半导体器件。 半导体器件包括第一晶体管，第二晶体管，第一绝缘体，第二绝缘体，第一布线和第一插塞。 第一晶体管包括硅。 第二晶体管包括氧化物半导体。 第一绝缘体位于第一晶体管的上方。 第二绝缘体位于第一绝缘体之上。 第二晶体管位于第二绝缘体上。 第一布线位于第二绝缘体和第一插头上。 第一晶体管和第二晶体管通过第一布线和第一插头彼此电连接。 第一布线具有低的透气性。 第二绝缘体的氢渗透性低于第一绝缘体的氢渗透性。

公开(公告)号：US20160173096A1

公开(公告)日：2016-06-16

申请号：US14967553

申请日：2015-12-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hiroki INOUE ,  Takanori MATSUZAKI ,  Shuhei NAGATSUKA ,  Takahiko ISHIZU ,  Tatsuya ONUKI

IPC: H03K19/0185 ,  H03K19/00

CPC classification number: H03K19/018521 ,  H03K3/356104 ,  H03K19/0016

Abstract: To provide a semiconductor device that inhibits unexpected output of a high-level signal immediately after the rise of a power supply voltage. A semiconductor device includes a first buffer circuit, a level shifter circuit, and a second buffer circuit. A first potential is supplied to the first buffer circuit, and a second potential is supplied to the level shifter circuit and the second buffer circuit; consequently, the semiconductor device returns to a normal state. The first potential is supplied to the first buffer circuit before the second potential is supplied to the level shifter circuit and the second buffer circuit, whereby the operations of the level shifter circuit and the second buffer circuit can be controlled. This inhibits unexpected output of a high-level signal to a wiring connected to the second buffer circuit.

Abstract translation: 提供在电源电压上升之后立即抑制高电平信号的意外输出的半导体器件。 半导体器件包括第一缓冲电路，电平移位器电路和第二缓冲电路。 第一电位被提供给第一缓冲电路，第二电位被提供给电平移位器电路和第二缓冲电路; 因此，半导体器件返回到正常状态。 在将第二电位提供给电平移位器电路和第二缓冲电路之前，将第一电位提供给第一缓冲电路，由此可以控制电平移位器电路和第二缓冲电路的操作。 这阻止了高电平信号对连接到第二缓冲电路的布线的意外输出。

公开(公告)号：US20150263007A1

公开(公告)日：2015-09-17

申请号：US14645566

申请日：2015-03-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Yutaka SHIONOIRI ,  Tomoaki ATSUMI ,  Shuhei NAGATSUKA ,  Yutaka OKAZAKI ,  Suguru HONDO

IPC: H01L27/105 ,  H01L29/04 ,  H01L29/24 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L29/045 ,  H01L27/0688 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/24 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device with a transistor having favorable electrical characteristics is provided. The semiconductor device has a memory circuit and a circuit that are over the same substrate. The memory circuit includes a capacitor, a first transistor, and a second transistor. A gate of the first transistor is electrically connected to the capacitor and one of a source and a drain of the second transistor. The circuit includes a third transistor and a fourth transistor that are electrically connected to each other in series. The first transistor and the third transistor each include an active layer including silicon, and the second transistor and the fourth transistor each include an active layer including an oxide semiconductor.

Abstract translation: 提供一种具有良好电特性的晶体管的半导体器件。 半导体器件具有位于相同衬底上的存储器电路和电路。 存储电路包括电容器，第一晶体管和第二晶体管。 第一晶体管的栅极电连接到电容器和第二晶体管的源极和漏极之一。 电路包括串联电连接的第三晶体管和第四晶体管。 第一晶体管和第三晶体管各自包括含有硅的有源层，第二晶体管和第四晶体管各自包括包含氧化物半导体的有源层。

公开(公告)号：US20140368486A1

公开(公告)日：2014-12-18

申请号：US14477221

申请日：2014-09-04

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuki HATA ,  Jun KOYAMA ,  Shuhei NAGATSUKA ,  Akihiro KIMURA

IPC: G09G3/20

CPC classification number: G09G3/2096 ,  G06F3/14 ,  G06F3/147 ,  G09G3/2092 ,  G09G2330/02 ,  G09G2370/16 ,  G09G2380/04 ,  G09G2380/06 ,  H04N5/66

Abstract: An object of the present invention is to provide a display device which does not need an input/output terminal such as an FPC or a cable for connecting to the display device and inputting an image signal to the display device directly, and can provide a setting, a display image, and the like which an operator desires. A display device of the present invention includes a display portion, a console portion to operate or input from the exterior, an antenna portion to transmit and receive a radio signal, a controller portion to control a signal input into the console portion and a signal for being transmitted or received in the antenna portion, and a battery portion to convert the radio signal received in the antenna portion into electric power and retain the electric power for driving the display portion.

Abstract translation: 本发明的目的是提供一种显示装置，其不需要诸如FPC或电缆的输入/输出端子来连接到显示装置并且直接将图像信号输入到显示装置，并且可以提供设置 ，显示图像等。 本发明的显示装置包括显示部分，从外部操作或输入的控制台部分，用于发送和接收无线电信号的天线部分，控制部分，用于控制输入到控制台部分的信号，以及用于 在天线部分中被发送或接收，以及电池部分，用于将在天线部分中接收的无线电信号转换为电力并保持用于驱动显示部分的电力。

公开(公告)号：US20230371286A1

公开(公告)日：2023-11-16

申请号：US18225186

申请日：2023-07-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tomoaki ATSUMI ,  Shuhei NAGATSUKA ,  Tamae MORIWAKA ,  Yuta ENDO

IPC: H10B69/00 ,  H01L29/786 ,  H01L27/06 ,  G11C7/16 ,  G11C8/14 ,  G11C11/403 ,  G11C11/408 ,  H10B41/20 ,  H10B41/70 ,  G11C11/24 ,  H01L29/24

CPC classification number: H10B69/00 ,  H01L29/7869 ,  H01L27/0688 ,  G11C7/16 ,  G11C8/14 ,  G11C11/403 ,  G11C11/4085 ,  H10B41/20 ,  H10B41/70 ,  G11C11/24 ,  H01L29/24

Abstract: [Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed.
[Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j≥2, the jth sub memory cell is arranged over the j−1th sub memory cell.

公开(公告)号：US20210081023A1

公开(公告)日：2021-03-18

申请号：US17104460

申请日：2020-11-25

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shuhei MAEDA ,  Shuhei NAGATSUKA ,  Tatsuya ONUKI ,  Kiyoshi KATO

IPC: G06F1/3234 ,  G11C16/30 ,  G11C14/00 ,  G11C5/14

Abstract: To reduce the area of a memory cell having a backup function. A storage device includes a cell array, and a row circuit and a column circuit that drive the cell array. The cell array includes a first power supply line, a second power supply line, a word line, a pair of bit lines, a memory cell, and a backup circuit. The cell array is located in a power domain where power gating can be performed. In the power gating sequence of the cell array, data in the memory cell is backed up to the backup circuit. The backup circuit is stacked over a region where the memory cell is formed. A plurality of wiring layers are provided between the backup circuit and the memory cell. The first power supply line, the second power supply line, the word line, and the pair of bit lines are located in different wiring layers.