公开(公告)号：US20200371922A1

公开(公告)日：2020-11-26

申请号：US16882272

申请日：2020-05-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen Bhoria ,  Timothy David Anderson ,  Pete Michael Hippleheuser

IPC: G06F12/0811 ,  G06F12/0895 ,  G06F12/0891 ,  G06F13/16 ,  G06F9/54 ,  G11C7/10 ,  G11C29/42 ,  G11C29/44

Abstract: Methods, apparatus, systems and articles of manufacture to facilitate atomic compare and swap in cache for a coherent level 1 data cache system are disclosed. An example system includes a cache storage; a cache controller coupled to the cache storage wherein the cache controller is operable to: receive a memory operation that specifies a key, a memory address, and a first set of data; retrieve a second set of data corresponding to the memory address; compare the second set of data to the key; based on the second set of data corresponding to the key, cause the first set of data to be stored at the memory address; and based on the second set of data not corresponding to the key, complete the memory operation without causing the first set of data to be stored at the memory address.

公开(公告)号：US20200371911A1

公开(公告)日：2020-11-26

申请号：US16882225

申请日：2020-05-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen Bhoria ,  Timothy David Anderson ,  Pete Michael Hippleheuser

IPC: G06F12/0817

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed facilitate read-modify-write support in a coherent victim cache with parallel data paths. An example apparatus includes a random-access memory configured to be coupled to a central processing unit via a first interface and a second interface, the random-access memory configured to obtain a read request indicating a first address to read via a snoop interface, an address encoder coupled to the random-access memory, the address encoder to, when the random-access memory indicates a hit of the read request, generate a second address corresponding to a victim cache based on the first address, and a multiplexer coupled to the victim cache to transmit a response including data obtained from the second address of the victim cache.

公开(公告)号：US20140122810A1

公开(公告)日：2014-05-01

申请号：US13660003

申请日：2012-10-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen Bhoria ,  Raguram Damodaran

IPC: G06F12/08

CPC classification number: G06F12/0811 ,  G06F12/0891

Abstract: A method to eliminate the delay of multiple overlapping block invalidate operations in a multi CPU environment by overlapping the block invalidate operation with normal CPU accesses, thus making the delay transparent. The cache controller performing the block invalidate operation merges multiple overlapping requests into a parallel stream to eliminate execution delays. Cache operations other that block invalidate, such as block write back or block write back invalidate may also be merged into the execution stream.

Abstract translation: 通过将块无效操作与正常的CPU访问重叠来消除多CPU环境中多个重叠块无效操作的延迟的方法，从而使延迟透明。 执行块无效操作的高速缓存控制器将多个重叠的请求合并到并行流中以消除执行延迟。 缓存操作其他块无效，如块写回或块写回无效也可以合并到执行流中。

公开(公告)号：US20240411703A1

公开(公告)日：2024-12-12

申请号：US18813178

申请日：2024-08-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy D. Anderson ,  Joseph Zbiciak ,  Duc Quang Bui ,  Abhijeet Chachad ,  Kai Chirca ,  Naveen Bhoria ,  Matthew D. Pierson ,  Daniel Wu ,  Ramakrishnan Venkatasubramanian

IPC: G06F12/1045 ,  G06F7/24 ,  G06F7/487 ,  G06F7/499 ,  G06F7/53 ,  G06F7/57 ,  G06F9/30 ,  G06F9/32 ,  G06F9/345 ,  G06F9/38 ,  G06F9/48 ,  G06F11/00 ,  G06F11/10 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1009 ,  G06F15/78 ,  G06F17/16 ,  H03H17/06

Abstract: Disclosed embodiments include an electronic device having a processor core, a memory, a register, and a data load unit to receive a plurality of data elements stored in the memory in response to an instruction. All of the data elements hare the same data size, which is specified by one or more coding bits. The data load unit includes an address generator to generate addresses corresponding to locations in the memory at which the data elements are located, and a formatting unit to format the data elements. The register is configured to store the formatted data elements, and the processor core is configured to receive the formatted data elements from the register.

公开(公告)号：US12147353B2

公开(公告)日：2024-11-19

申请号：US16882235

申请日：2020-05-22

Applicant: Texas Instruments Incorporated

Inventor： Naveen Bhoria ,  Timothy David Anderson ,  Pete Michael Hippleheuser

IPC: G06F12/128 ,  G06F9/30 ,  G06F9/54 ,  G06F11/10 ,  G06F12/02 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0853 ,  G06F12/0855 ,  G06F12/0864 ,  G06F12/0884 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/12 ,  G06F12/121 ,  G06F12/126 ,  G06F12/127 ,  G06F13/16 ,  G06F15/80 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C29/42 ,  G11C29/44

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for read-modify-write support in multi-banked data RAM cache for bank arbitration. An example data cache system includes a store queue including a plurality of bank queues including a first bank queue having a write and read port configured to receive a respective write and read operation, storage coupled to the store queue including a plurality of data banks including a first data bank having a first port configured to receive the write or the read operation, first through third multiplexers, and bank arbitration logic including first arbiters including a first arbiter and second arbiters including a second arbiter, the first arbiter coupled to the second arbiter, the second and third multiplexers, the second arbiter coupled to the first multiplexer.

公开(公告)号：US20240362166A1

公开(公告)日：2024-10-31

申请号：US18305437

申请日：2023-04-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen Bhoria ,  Timothy David Anderson ,  Pete Michael Hippleheuser

IPC: G06F12/0891 ,  G06F12/1027

CPC classification number: G06F12/0891 ,  G06F12/1027

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to forward and invalidate inflight data in a store queue. An example apparatus includes a cache storage, a cache controller coupled to the cache storage and operable to receive a first memory operation, determine that the first memory operation corresponds to a read miss in the cache storage, determine a victim address in the cache storage to evict in response to the read miss, issue a read-invalidate command that specifies the victim address, compare the victim address to a set of addresses associated with a set of memory operations being processed by the cache controller, and in response to the victim address matching a first address of the set of addresses corresponding to a second memory operation of the set of memory operations, provide data associated with the second memory operation.

公开(公告)号：US11940930B2

公开(公告)日：2024-03-26

申请号：US17875572

申请日：2022-07-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen Bhoria ,  Timothy David Anderson ,  Pete Michael Hippleheuser

IPC: G06F9/30 ,  G06F9/54 ,  G06F11/10 ,  G06F12/02 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0853 ,  G06F12/0855 ,  G06F12/0864 ,  G06F12/0884 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/12 ,  G06F12/121 ,  G06F12/126 ,  G06F12/127 ,  G06F12/128 ,  G06F13/16 ,  G06F15/80 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C29/42 ,  G11C29/44

CPC classification number: G06F12/128 ,  G06F9/3001 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/546 ,  G06F11/1064 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0292 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/082 ,  G06F12/0853 ,  G06F12/0855 ,  G06F12/0864 ,  G06F12/0884 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/12 ,  G06F12/121 ,  G06F12/126 ,  G06F12/127 ,  G06F13/1605 ,  G06F13/1642 ,  G06F13/1673 ,  G06F13/1689 ,  G06F15/8069 ,  G11C5/066 ,  G11C7/10 ,  G11C7/1015 ,  G11C7/106 ,  G11C7/1075 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/222 ,  G11C29/42 ,  G11C29/44 ,  G06F2212/1016 ,  G06F2212/1021 ,  G06F2212/1024 ,  G06F2212/1041 ,  G06F2212/1044 ,  G06F2212/301 ,  G06F2212/454 ,  G06F2212/6032 ,  G06F2212/6042 ,  G06F2212/608 ,  G06F2212/62

Abstract: Methods, apparatus, systems and articles of manufacture to facilitate atomic operation in victim cache are disclosed. An example system includes a first cache storage to store a first set of data; a second cache storage to store a second set of data that has been evicted from the first cache storage; and a storage queue coupled to the first cache storage and the second cache storage, the storage queue including: an arithmetic component to: receive the second set of data from the second cache storage in response to a memory operation; and perform an arithmetic operation on the second set of data to produce a third set of data; and an arbitration manager to store the third set of data in the second cache storage.

公开(公告)号：US20240020242A1

公开(公告)日：2024-01-18

申请号：US18362015

申请日：2023-07-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen Bhoria ,  Timothy David Anderson ,  Pete Michael Hippleheuser

IPC: G06F12/126 ,  G06F12/0888 ,  G06F12/0891 ,  G06F9/54 ,  G06F12/02 ,  G06F12/0811 ,  G06F12/128 ,  G06F12/0817 ,  G06F12/0804 ,  G06F9/30 ,  G11C7/10 ,  G11C29/42 ,  G11C29/44 ,  G06F11/10 ,  G06F12/0855 ,  G06F12/12 ,  G06F12/0806 ,  G06F12/0815 ,  G06F12/0853 ,  G06F13/16 ,  G06F12/121 ,  G06F12/0884 ,  G06F12/0897 ,  G06F12/0895 ,  G06F12/0864 ,  G11C7/22 ,  G11C5/06 ,  G06F15/80 ,  G06F12/0802

CPC classification number: G06F12/126 ,  G06F2212/6042 ,  G06F12/0891 ,  G06F9/546 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0811 ,  G06F12/128 ,  G06F12/082 ,  G06F12/0804 ,  G06F9/3001 ,  G06F9/30047 ,  G11C7/106 ,  G11C7/1087 ,  G11C29/42 ,  G11C29/44 ,  G06F11/1064 ,  G06F12/0855 ,  G06F12/12 ,  G06F12/0806 ,  G06F12/0815 ,  G06F12/0853 ,  G06F13/1605 ,  G06F12/121 ,  G06F12/0292 ,  G06F12/0884 ,  G06F12/0897 ,  G06F12/0895 ,  G06F12/0864 ,  G11C7/222 ,  G11C7/1075 ,  G11C7/1078 ,  G06F13/1642 ,  G06F13/1673 ,  G06F13/1689 ,  G11C5/066 ,  G11C7/10 ,  G11C7/1015 ,  G06F15/8069 ,  G06F12/0802 ,  G06F9/30043 ,  G06F2212/1021 ,  G06F2212/608 ,  G06F2212/6032 ,  G06F2212/1024 ,  G06F2212/62 ,  G06F2212/1016 ,  G06F2212/1041 ,  G06F2212/1044 ,  G06F2212/301 ,  G06F2212/454 ,  G06F12/0888

Abstract: Methods, apparatus, systems and articles of manufacture to reduce bank pressure using aggressive write merging are disclosed. An example apparatus includes a first cache storage; a second cache storage; a store queue coupled to at least one of the first cache storage and the second cache storage and operable to: receive a first memory operation; process the first memory operation for storing the first set of data in at least one of the first cache storage and the second cache storage; receive a second memory operation; and prior to storing the first set of data in the at least one of the first cache storage and the second cache storage, merge the first memory operation and the second memory operation.

公开(公告)号：US11803382B2

公开(公告)日：2023-10-31

申请号：US17901940

申请日：2022-09-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen Bhoria ,  Duc Bui ,  Dheera Balasubramanian Samudrala ,  Rama Venkatasubramanian

IPC: G06F9/30 ,  G11C11/409 ,  G06F12/02 ,  G06F9/38

CPC classification number: G06F9/30145 ,  G06F9/3001 ,  G06F9/30007 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/30101 ,  G06F9/30105 ,  G06F9/3818 ,  G06F12/0246 ,  G06F12/0292 ,  G11C11/409

Abstract: A digital data processor includes a multi-stage butterfly network, which is configured to, in response to a look up table read instruction, receive look up table data from an intermediate register, reorder the look up table data based on control signals comprising look up table configuration register data, and write the reordered look up table data to a destination register specified by the look up table read instruction.

公开(公告)号：US11782718B2

公开(公告)日：2023-10-10

申请号：US17216821

申请日：2021-03-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen Bhoria ,  Kai Chirca ,  Timothy D. Anderson ,  Duc Bui ,  Abhijeet A. Chachad ,  Son Hung Tran

IPC: G06F9/30 ,  G06F9/38 ,  G06F11/00 ,  G06F12/0897 ,  G06F12/0875 ,  G06F9/32 ,  G06F11/10 ,  G06F9/345 ,  G06F12/0811

CPC classification number: G06F9/3016 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/32 ,  G06F9/345 ,  G06F9/3802 ,  G06F9/383 ,  G06F9/3834 ,  G06F9/3867 ,  G06F9/3877 ,  G06F11/00 ,  G06F11/1048 ,  G06F12/0875 ,  G06F12/0897 ,  G06F9/3822 ,  G06F11/10 ,  G06F12/0811 ,  G06F2212/452 ,  G06F2212/60

Abstract: Techniques related to executing a plurality of instructions by a processor comprising receiving a first instruction configured to cause the processor to output a first data value to a first address in a first data cache, outputting, by the processor, the first data value to a second address in a second data cache, receiving a second instruction configured to cause a streaming engine associated with the processor to prefetch data from the first data cache, determining that the first data value has not been outputted from the second data cache to the first data cache, stalling execution of the second instruction, receiving an indication, from the second data cache, that the first data value has been output from the second data cache to the first data cache, and resuming execution of the second instruction based on the received indication.