公开(公告)号：US11854986B2

公开(公告)日：2023-12-26

申请号：US17809961

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Wei-Kang Hsieh ,  Shih-Wei Chen ,  Tin-Hao Kuo ,  Hao-Yi Tsai

IPC: H01L23/40 ,  H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L21/768 ,  H01L25/065 ,  H01L21/56 ,  H01L23/367

CPC classification number: H01L23/5384 ,  H01L21/56 ,  H01L21/76802 ,  H01L23/31 ,  H01L23/367 ,  H01L23/4006 ,  H01L23/4012 ,  H01L23/5385 ,  H01L24/14 ,  H01L25/0657

Abstract: A semiconductor device includes a die, an encapsulant over a front-side surface of the die, a redistribution structure on the encapsulant, a thermal module coupled to the back-side surface of the die, and a bolt extending through the redistribution structure and the thermal module. The die includes a chamfered corner. The bolt is adjacent to the chamfered corner.

公开(公告)号：US11848235B2

公开(公告)日：2023-12-19

申请号：US17870075

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Wei Ling Chang ,  Chuei-Tang Wang ,  Tin-Hao Kuo ,  Che-Wei Hsu

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/77 ,  H01L23/00 ,  H01L25/18 ,  H01L23/40

CPC classification number: H01L21/76895 ,  H01L21/76898 ,  H01L21/77 ,  H01L23/528 ,  H01L24/03 ,  H01L24/06 ,  H01L25/18 ,  H01L23/4006 ,  H01L2023/4087 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/06182 ,  H01L2224/16145

Abstract: Systems, devices and methods of manufacturing a system on silicon wafer (SoSW) device and package are described herein. A plurality of functional dies is formed in a silicon wafer. Different sets of masks are used to form different types of the functional dies in the silicon wafer. A first redistribution structure is formed over the silicon wafer and provides local interconnects between adjacent dies of the same type and/or of different types. A second redistribution structure may be formed over the first redistribution layer and provides semi-global and/or global interconnects between non-adjacent dies of the same type and/or of different types. An optional backside redistribution structure may be formed over a second side of the silicon wafer opposite the first redistribution layer. The optional backside redistribution structure may provide backside interconnects between functional dies of different types.

公开(公告)号：US11842955B2

公开(公告)日：2023-12-12

申请号：US17852766

申请日：2022-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Hung-Jui Kuo ,  Ming-Che Ho ,  Tzung-Hui Lee

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/48 ,  H01L23/485 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10

CPC classification number: H01L23/49811 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/481 ,  H01L23/485 ,  H01L24/19 ,  H01L24/20 ,  H01L24/83 ,  H01L21/561 ,  H01L23/3128 ,  H01L24/05 ,  H01L24/13 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/13082 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13149 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13184 ,  H01L2224/18 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73267 ,  H01L2224/83815 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/1203 ,  H01L2924/1304 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/1304 ,  H01L2924/00012 ,  H01L2924/1203 ,  H01L2924/00012

Abstract: An integrated circuit package and a method of forming the same are provided. A method includes forming a first redistribution layer over a carrier, the first redistribution layer including a contact pad and a bond pad. A conductive pillar is formed over the contact pad. A backside surface of an integrated circuit die is attached to the bond pad using a solder joint. An encapsulant is formed along a sidewall of the conductive pillar and a sidewall of the integrated circuit die, a front-side surface of the integrated circuit die being substantially level with a topmost surface of the encapsulant and a topmost surface of the conductive pillar. A second redistribution layer is formed over the front-side surface of the integrated circuit die, the topmost surface of the encapsulant and the topmost surface of the conductive pillar.

公开(公告)号：US20230386919A1

公开(公告)日：2023-11-30

申请号：US18446748

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun Yi Wu ,  Chen-Hua Yu

IPC: H01L21/768 ,  H01L21/56 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L21/76895 ,  H01L21/561 ,  H01L21/486 ,  H01L24/19 ,  H01L24/32 ,  H01L24/33 ,  H01L25/50 ,  H01L25/0657 ,  H01L24/94 ,  H01L24/05 ,  H01L2924/181 ,  H01L2224/33181 ,  H01L2224/32145 ,  H01L2224/2101

Abstract: In an embodiment, a structure includes a core substrate, a redistribution structure coupled to a first side of the core substrate, the redistribution structure including a plurality of redistribution layers, each of the plurality of redistribution layers comprising a dielectric layer and a metallization layer, and a first local interconnect component embedded in a first redistribution layer of the plurality of redistribution layers, the first local interconnect component including a substrate, an interconnect structure on the substrate, and bond pads on the interconnect structure, the bond pads of the first local interconnect component physically contacting a metallization layer of a second redistribution layer, the second redistribution layer being adjacent the first redistribution layer, the metallization layer of the second redistribution layer comprising first conductive vias, the dielectric layer of the first redistribution layer encapsulating the first local interconnect component.

公开(公告)号：US20230384543A1

公开(公告)日：2023-11-30

申请号：US17896249

申请日：2022-08-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsing-Kuo Hsia ,  Chih-Kuang Yu ,  Chen-Hua Yu ,  Jui Lin Chao

IPC: G02B6/42

CPC classification number: G02B6/4271 ,  G02B6/4245 ,  G02B6/4206

Abstract: A method includes bonding a photonic engine onto an interposer, and bonding a package component onto the interposer. The package component includes a device die. The method further includes encapsulating the package component and the photonic engine in an encapsulant, attaching a thermal-electronic cooler to the photonic engine, and attaching a metal lid to the package component.

公开(公告)号：US20230369303A1

公开(公告)日：2023-11-16

申请号：US18357457

申请日：2023-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chia Lai ,  Cheng-Chieh Hsieh ,  Tin-Hao Kuo ,  Hao-Yi Tsai ,  Chung-Shi Liu ,  Chen-Hua Yu

IPC: H01L25/16 ,  H01L21/56 ,  H01L23/00 ,  H01L23/40 ,  H01L23/31

CPC classification number: H01L25/16 ,  H01L21/561 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L24/73 ,  H01L23/4012 ,  H01L23/3107 ,  H01L2924/1434 ,  H01L2023/4087 ,  H01L2224/25171 ,  H01L2224/24147 ,  H01L2224/24137 ,  H01L2224/2518 ,  H01L2224/73209 ,  H01L2924/1205 ,  H01L2924/1431

Abstract: A package includes a first package and a second package over and bonded to the first package. The first package includes a first device die, and a first encapsulant encapsulating the first device die therein. The second package includes an Independent Passive Device (IPD) die, and a second encapsulant encapsulating the IPD die therein. The package further includes a power module over and bonded to the second package.

公开(公告)号：US20230369254A1

公开(公告)日：2023-11-16

申请号：US18359273

申请日：2023-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Chen-Hua Yu ,  Kuo Lung Pan ,  Tin-Hao Kuo ,  Hao-Yi Tsai

IPC: H01L23/64 ,  H01L21/683 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/645 ,  H01L21/6835 ,  H01L21/4853 ,  H01L23/5386 ,  H01L21/4857 ,  H01L24/20 ,  H01L23/5389 ,  H01L23/3128 ,  H01L21/565 ,  H01L23/5383 ,  H01L21/568 ,  H01L24/19 ,  H01L2224/214 ,  H01L2924/19042 ,  H01L2924/19103 ,  H01L2221/68372 ,  H01L2924/1903 ,  H01L2924/1437

Abstract: A semiconductor device includes a first plurality of dies encapsulated by an encapsulant, an interposer over the first plurality of dies, an interconnect structure over and electrically connected to the interposer, and a plurality of conductive pads on a surface of the interconnect structure opposite the interposer. The interposer includes a plurality of embedded passive components. Each die of the first plurality of dies is electrically connected to the interposer. The interconnect structure includes a solenoid inductor in a metallization layer of the interconnect structure.

公开(公告)号：US11810831B2

公开(公告)日：2023-11-07

申请号：US17872488

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chih-Wei Wu ,  Ying-Ching Shih ,  Szu-Wei Lu

IPC: H01L23/31 ,  H01L25/065 ,  H01L21/56 ,  H01L25/00 ,  H01L23/18 ,  H01L21/822 ,  H01L25/11

CPC classification number: H01L23/3135 ,  H01L21/56 ,  H01L23/18 ,  H01L25/0657 ,  H01L25/50 ,  H01L21/563 ,  H01L21/568 ,  H01L21/8221 ,  H01L25/117 ,  H01L2225/06513

Abstract: An integrated circuit package and a method of forming the same are provided. A method includes stacking a plurality of integrated circuit dies on a wafer to form a die stack. A bonding process is performed on the die stack. The bonding process mechanically and electrically connects adjacent integrated circuit dies of the die stack to each other. A dam structure is formed over the wafer. The dam structure surrounds the die stack. A first encapsulant is formed over the wafer and between the die stack and the dam structure. The first encapsulant fills gaps between the adjacent integrated circuit dies of the die stack. A second encapsulant is formed over the wafer. The second encapsulant surrounds the die stack, the first encapsulant and the dam structure.

公开(公告)号：US11798925B2

公开(公告)日：2023-10-24

申请号：US17396993

申请日：2021-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chia Lai ,  Cheng-Chieh Hsieh ,  Tin-Hao Kuo ,  Hao-Yi Tsai ,  Chung-Shi Liu ,  Chen-Hua Yu

IPC: H01L25/16 ,  H01L21/56 ,  H01L23/31 ,  H01L23/40 ,  H01L23/00

CPC classification number: H01L25/16 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/4012 ,  H01L24/24 ,  H01L24/25 ,  H01L24/73 ,  H01L24/82 ,  H01L2023/4087 ,  H01L2224/24137 ,  H01L2224/24147 ,  H01L2224/2518 ,  H01L2224/25171 ,  H01L2224/73209 ,  H01L2924/1205 ,  H01L2924/1431 ,  H01L2924/1434

Abstract: A package includes a first package and a second package over and bonded to the first package. The first package includes a first device die, and a first encapsulant encapsulating the first device die therein. The second package includes an Independent Passive Device (IPD) die, and a second encapsulant encapsulating the IPD die therein. The package further includes a power module over and bonded to the second package.

公开(公告)号：US11784172B2

公开(公告)日：2023-10-10

申请号：US17232325

申请日：2021-04-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chung-Hao Tsai ,  Chuei-Tang Wang ,  Chieh-Yen Chen

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/48 ,  H01L21/304 ,  H01L21/683 ,  H01L21/768

CPC classification number: H01L25/16 ,  H01L21/304 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L2221/68327 ,  H01L2224/05124 ,  H01L2224/08145 ,  H01L2224/80006 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1205 ,  H01L2924/1434

Abstract: A method includes bonding a capacitor die to a device die. The device die includes a first semiconductor substrate, active devices at a surface of the first semiconductor substrate, a plurality of low-k dielectric layers, a first dielectric layer over and contacting a top low-k dielectric layer in the plurality of low-k dielectric layers, and a first plurality of bond pads in the first dielectric layer. The capacitor die includes a second dielectric layer bonding to the first dielectric layer, a second plurality of bond pads in the second dielectric layer and bonding to the first plurality of bond pads, and a capacitor electrically coupled to the second plurality of bond pads. After the capacitor die is bonded to the device die, an aluminum-containing pad is formed over the capacitor die and electrically coupled to the device die. A polymer layer is formed over the aluminum-containing pad.