公开(公告)号：US20080268572A1

公开(公告)日：2008-10-30

申请号：US12169132

申请日：2008-07-08

申请人： Geng-Shin Shen ,  David Wei Wang

发明人： Geng-Shin Shen ,  David Wei Wang

IPC分类号： H01L21/58

CPC分类号： H01L24/16 ,  H01L24/28 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/90 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73104 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/83136 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/83856 ,  H01L2224/85 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A fabricating process of chip package structure is provided. First, a first substrate having a plurality of first bonding pads and a second substrate having a plurality of second bonding pads are provide, wherein a plurality of bumps are formed on the first bonding pads of the first substrate. A first two-stage adhesive layer is formed on the first substrate or on the second substrate and is B-stagized to form a first B-staged adhesive layer. A second two-stage adhesive layer is formed on the first B-staged adhesive layer and is B-stagized to form a second B-staged adhesive layer. Then, the first substrate and the second substrate are bonded via the first B-staged adhesive layer and the second B-staged adhesive layer such that each of the first bonding pads is respectively electrically connected to one of the second bonding pads via one of the bumps.

摘要翻译： 提供了芯片封装结构的制造工艺。 首先，提供具有多个第一接合焊盘的第一基板和具有多个第二接合焊盘的第二基板，其中在第一基板的第一接合焊盘上形成多个凸点。 在第一基板上或第二基板上形成第一两级粘合剂层，并且被B阶段化以形成第一B阶粘合剂层。 在第一B阶粘合剂层上形成第二两层粘合剂层，并且被B阶段化以形成第二B阶粘合剂层。 然后，第一基板和第二基板经由第一B阶粘合剂层和第二B阶粘合剂层接合，使得每个第一接合焊盘分别经由第一接合焊盘中的一个电连接到第二接合焊盘中的一个 颠簸

公开(公告)号：US07385282B2

公开(公告)日：2008-06-10

申请号：US11255710

申请日：2005-10-19

申请人： Geng-Shin Shen

发明人： Geng-Shin Shen

IPC分类号： H01L23/02

CPC分类号： H01L25/0657 ,  H01L24/73 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/731 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

摘要： A stacked-type chip package structure including a substrate, a first chip, bonding wires, a second chip and B-stage conductive bumps is provided. The first chip is disposed on the substrate, and it has first bonding pads disposed on an active surface thereof. Besides, the first bonding pads are electrically connected to the substrate through the bonding wires. The second chip is disposed above the first chip, and it has second bonding pads disposed on an active surface thereof. The second bonding pads of the second chip are electrically connected to the first bonding pads of the first chip through the B-stage conductive bumps respectively, and each B-stage conductive bump covers a portion of the corresponding bonding wire.

摘要翻译： 提供了包括基板，第一芯片，接合线，第二芯片和B级导电凸块的堆叠型芯片封装结构。 第一芯片设置在基板上，并且其第一接合焊盘设置在其有效表面上。 此外，第一接合焊盘通过接合线电连接到基板。 第二芯片设置在第一芯片上方，并且其第二焊盘设置在其活性表面上。 第二芯片的第二焊盘分别通过B级导电凸块电连接到第一芯片的第一焊盘，并且每个B级导电凸块覆盖相应接合线的一部分。

公开(公告)号：US20070152317A1

公开(公告)日：2007-07-05

申请号：US11684543

申请日：2007-03-09

申请人： Geng-Shin Shen

发明人： Geng-Shin Shen

IPC分类号： H01L23/02

CPC分类号： H01L25/0657 ,  H01L24/73 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/731 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

摘要： A stacked-type chip package structure including a substrate, a first chip, bonding wires, a second chip and B-stage conductive bumps is provided. The first chip is disposed on the substrate, and it has first bonding pads disposed on an active surface thereof. Besides, the first bonding pads are electrically connected to the substrate through the bonding wires. The second chip is disposed above the first chip, and it has second bonding pads disposed on an active surface thereof. The second bonding pads of the second chip are electrically connected to the first bonding pads of the first chip through the B-stage conductive bumps respectively, and each B-stage conductive bump covers a portion of the corresponding bonding wire.

摘要翻译： 提供了包括基板，第一芯片，接合线，第二芯片和B级导电凸块的堆叠型芯片封装结构。 第一芯片设置在基板上，并且其第一接合焊盘设置在其有效表面上。 此外，第一接合焊盘通过接合线电连接到基板。 第二芯片设置在第一芯片上方，并且其第二焊盘设置在其活性表面上。 第二芯片的第二焊盘分别通过B级导电凸块电连接到第一芯片的第一焊盘，并且每个B级导电凸块覆盖相应接合线的一部分。

公开(公告)号：US20070085176A1

公开(公告)日：2007-04-19

申请号：US11352001

申请日：2006-02-10

申请人： Wu-Chang Tu ,  Geng-Shin Shen

发明人： Wu-Chang Tu ,  Geng-Shin Shen

IPC分类号： H01L23/495

CPC分类号： H01L23/3107 ,  H01L23/4951 ,  H01L23/49541 ,  H01L23/49551 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： A chip package having asymmetric molding includes a lead frame, a chip, an adhesive layer, bonding wires and a molding compound. The lead frame includes a turbulent plate and a frame body having inner lead portions and outer lead portions. The turbulent plate is bended downwards to form a concave portion. The first end of the turbulent plate is connected to the frame body, and the second end is lower than the inner lead portions. The chip is fixed under the inner lead portions through the adhesive layer. The bonding wires are connected between the chip and the inner lead portions. The molding compound encapsulates the chip, the bonding wires, and the turbulent plate. The ratio between the thickness of the molding compound over and under the concave portion is larger than 1. The thickness of the molding compound under and over the outer lead portions is not equal.

摘要翻译： 具有不对称模制的芯片封装包括引线框架，芯片，粘合剂层，接合线和模塑料。 引线框架包括湍流板和具有内引线部分和外引线部分的框体。 湍流板向下弯曲以形成凹部。 湍流板的第一端连接到框体，第二端低于内引线部。 芯片通过粘合剂层固定在内引线部分的下方。 接合线连接在芯片和内引线部分之间。 模塑料封装芯片，接合线和湍流板。 凹形部分上方和下方的模塑料的厚度之比大于1.外引线部分之下和之上的模塑料的厚度不相等。

公开(公告)号：US20060208365A1

公开(公告)日：2006-09-21

申请号：US11202820

申请日：2005-08-12

申请人： Geng-Shin Shen ,  Tsai Hsien

发明人： Geng-Shin Shen ,  Tsai Hsien

IPC分类号： H01L23/48

CPC分类号： H01L21/563 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/4985 ,  H01L24/83 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83851 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/0401

摘要： A flip-chip-on-film package structure includes a flexible substrate, a flip chip, and a first heat sink. The flexible substrate has an upper surface and a lower surface. The flip chip is mounted on the upper surface of the flexible substrate and electrically connected to the flexible substrate. The first heat sink is disposed on the lower surface of the flexible substrate and used for dissipating the heat generated by the flip chip during operation. Moreover, the first heat sink can also improve the strength of the package structure.

摘要翻译： 薄膜封装结构包括柔性基板，倒装芯片和第一散热器。 柔性基板具有上表面和下表面。 倒装芯片安装在柔性基板的上表面上并电连接到柔性基板。 第一散热器设置在柔性基板的下表面上，用于在操作期间消散由倒装芯片产生的热量。 此外，第一散热器还可以提高封装结构的强度。

公开(公告)号：US08431478B2

公开(公告)日：2013-04-30

申请号：US13234842

申请日：2011-09-16

申请人： Geng-Shin Shen

发明人： Geng-Shin Shen

IPC分类号： H01L21/44

CPC分类号： H01L24/11 ,  H01L23/3114 ,  H01L23/3121 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/034 ,  H01L2224/036 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/11005 ,  H01L2224/111 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13541 ,  H01L2224/16237 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/814 ,  H01L2224/83104 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/206 ,  H01L2224/05552

摘要： A semiconductor package with improved height uniformity of solder cap bumps therein is disclosed. In one embodiment, the semiconductor package includes a semiconductor substrate comprising a plurality of pads spacedly disposed on a top surface of the substrate, and a passivation layer formed on top of the pads, wherein a plurality of pad openings are created to expose at least a portion of the pads; a plurality of solder cap bumps formed at the pad openings of the passivation layer; and a carrier substrate having a plurality of bond pads electrically connected to the solder caps of the solder cap bumps on the semiconductor substrate. The solder cap bump includes a solder cap on top of a conductive pillar, and a patternable layer can be coated and patterned on a top surface of the conductive pillar to define an area for the solder ball to be deposited. The deposited solder ball can be reflowed to form the solder cap.

摘要翻译： 公开了一种具有改善的焊料凸块高度均匀性的半导体封装。 在一个实施例中，半导体封装包括半导体衬底，其包括间隔地设置在衬底的顶表面上的多个衬垫以及形成在衬垫顶部上的钝化层，其中创建多个衬垫开口以暴露至少一个 垫的一部分; 形成在钝化层的焊盘开口处的多个焊料凸块; 以及载体基板，其具有与半导体基板上的焊料凸块的焊料帽电连接的多个接合焊盘。 焊料凸块包括在导电柱顶部的焊料帽，并且可以在导电柱的顶表面上涂覆和图案化图案化层以限定要沉积的焊球的区域。 沉积的焊球可以被回流以形成焊帽。

公开(公告)号：US08426255B2

公开(公告)日：2013-04-23

申请号：US13232946

申请日：2011-09-14

申请人： Geng-Shin Shen

发明人： Geng-Shin Shen

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L24/81 ,  H01L23/3107 ,  H01L23/4952 ,  H01L23/49548 ,  H01L23/49861 ,  H01L24/13 ,  H01L24/16 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/10175 ,  H01L2224/1134 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/14151 ,  H01L2224/14155 ,  H01L2224/16245 ,  H01L2224/16257 ,  H01L2224/16258 ,  H01L2224/81193 ,  H01L2224/81856 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/05552

摘要： A method for manufacturing a semiconductor package structure is disclosed. In one embodiment, the method includes the steps of forming a plurality of conductive pastes on a matrix lead frame with a groove located within a predetermined distance from each conductive paste on the lead; partially curing the conductive pastes so that the conductive pastes are in a semi-cured state; preparing at least one chip with a plurality of bumps thereon; electrically connecting the chip and the lead by implanting the bumps into the semi-cured conductive pastes, wherein the groove on the lead of the matrix lead frame is configured to receive overflowed semi-cured conductive pastes; curing the semi-cured conductive pastes to completely secure the bumped chip; and forming an encapsulating material covering the lead frame and the chip. The method can also be applied in pre-molded lead frame package.

摘要翻译： 公开了半导体封装结构的制造方法。 在一个实施例中，该方法包括以下步骤：在矩阵引线框架上形成多个导电浆料，其中凹槽位于与引线上的每个导电浆料预定距离内; 部分固化导电浆料，使得导电浆料处于半固化状态; 制备其上具有多个凸块的至少一个芯片; 通过将凸块植入到半固化的导电浆料中来将芯片和引线电连接，其中，矩阵引线框架的引线上的槽被配置为接收溢出的半固化的导电浆料; 固化半固化导电浆料以完全固定凸起的芯片; 以及形成覆盖引线框和芯片的封装材料。 该方法也可应用于预成型引线框架封装中。

公开(公告)号：US20130069231A1

公开(公告)日：2013-03-21

申请号：US13234842

申请日：2011-09-16

申请人： Geng-Shin Shen

发明人： Geng-Shin Shen

IPC分类号： H01L23/488 ,  H01L21/56 ,  H01L21/283

CPC分类号： H01L24/11 ,  H01L23/3114 ,  H01L23/3121 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/034 ,  H01L2224/036 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/11005 ,  H01L2224/111 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13541 ,  H01L2224/16237 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/814 ,  H01L2224/83104 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/206 ,  H01L2224/05552

摘要： A semiconductor package with improved height uniformity of solder cap bumps therein is disclosed. In one embodiment, the semiconductor package includes a semiconductor substrate comprising a plurality of pads spacedly disposed on a top surface of the substrate, and a passivation layer formed on top of the pads, wherein a plurality of pad openings are created to expose at least a portion of the pads; a plurality of solder cap bumps formed at the pad openings of the passivation layer; and a carrier substrate having a plurality of bond pads electrically connected to the solder caps of the solder cap bumps on the semiconductor substrate. The solder cap bump includes a solder cap on top of a conductive pillar, and a patternable layer can be coated and patterned on a top surface of the conductive pillar to define an area for the solder ball to be deposited. The deposited solder ball can be reflowed to form the solder cap.

摘要翻译： 公开了一种具有改善的焊料凸块高度均匀性的半导体封装。 在一个实施例中，半导体封装包括半导体衬底，其包括间隔地设置在衬底的顶表面上的多个衬垫以及形成在衬垫顶部上的钝化层，其中创建多个衬垫开口以暴露至少一个 垫的一部分; 形成在钝化层的焊盘开口处的多个焊料凸块; 以及载体基板，其具有与半导体基板上的焊料凸块的焊料帽电连接的多个接合焊盘。 焊料凸块包括在导电柱顶部的焊料帽，并且可以在导电柱的顶表面上涂覆和图案化图案化层以限定要沉积的焊球的区域。 沉积的焊球可以被回流以形成焊帽。

公开(公告)号：US08207603B2

公开(公告)日：2012-06-26

申请号：US12849188

申请日：2010-08-03

申请人： Geng-Shin Shen ,  Wu-Chang Tu

发明人： Geng-Shin Shen ,  Wu-Chang Tu

IPC分类号： H01L23/02 ,  H01L23/48

CPC分类号： H01L23/49541 ,  H01L23/49531 ,  H01L23/49551 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/4911 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/838 ,  H01L2224/92247 ,  H01L2225/06562 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： The present invention provides a stacked chip package structure with leadframe having inner leads with transfer pad, comprising: a leadframe composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, wherein the die pad is provided between the plurality of inner leads arranged in rows facing each other and vertically distant from the plurality of inner leads; an offset chip-stacked structure formed with a plurality of chips stacked together, the offest chip-stacked structure being set on the die pad and electrically connected to the plurality of inner leads arranged in rows facing each other; and an encapsulant covering the offset chip-stacked structure and the leadframe, the plurality of outer leads extending out of said encapsulant; the improvement of which being that the inner leads of the leadframe are coated with an insulating layer and a plurality of metal pads are selectively formed on the insulating layer.

摘要翻译： 本发明提供一种具有引线框架的堆叠式芯片封装结构，其具有带有传输焊盘的内引线，包括：引线框架，由相互排列成行的多个内引线，多个外引线和管芯焊盘构成， 衬垫设置在彼此相对并且彼此垂直远离多个内引线的行中排列的多个内引线之间; 叠置了多个芯片的偏置芯片堆叠结构，最小的芯片堆叠结构被设置在芯片焊盘上并电连接到彼此相对布置的多个内部引线; 以及覆盖所述偏移芯片堆叠结构和所述引线框的密封剂，所述多个外引线从所述密封剂延伸出来; 其改进之处在于引线框架的内引线被覆有绝缘层，并且绝缘层上选择性地形成多个金属焊盘。

公开(公告)号：US20120074402A1

公开(公告)日：2012-03-29

申请号：US13308828

申请日：2011-12-01

申请人： Jun-Yong Wang ,  Geng-Shin Shen

发明人： Jun-Yong Wang ,  Geng-Shin Shen

IPC分类号： H01L23/485

CPC分类号： H01L24/13 ,  H01L21/56 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1357 ,  H01L2224/13644 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2224/83192 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

摘要： This invention relates to a packaging structure and method for manufacturing the packaging structure. The packaging structure comprises a substrate film, a plurality of chips, a compound resin layer and a support layer. The substrate film is formed with circuits having a plurality of terminals exposed from a solder mask. The chips, each of which has a plurality of pads, under bump metals (UBMs) formed on the pads, and composite bumps disposed onto the UBMs, are bonded onto the substrate film to form the first tape. The second tape comprises the support layer and the compound resin layer formed on the support layer. The first tape and the second tape are both in reel-form and are expanded towards a pair of rollers to be heated and pressurized for encapsulating the chips.

摘要翻译： 本发明涉及用于制造包装结构的包装结构和方法。 包装结构包括基底膜，多个芯片，复合树脂层和支撑层。 衬底膜由具有从焊料掩模暴露的多个端子的电路形成。 每个芯片具有多个焊盘，形成在焊盘上的凸块下金属（UBM）和设置在UBM上的复合凸块相连接，形成第一条带。 第二带包括支撑层和形成在支撑层上的复合树脂层。 第一带和第二带都是卷状的并且朝向一对辊膨胀，以被加热和加压以封装芯片。