公开(公告)号：US08298875B1

公开(公告)日：2012-10-30

申请号：US13041404

申请日：2011-03-06

申请人： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Paul Lim

发明人： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Paul Lim

IPC分类号： H01L21/20

CPC分类号： H01L27/249 ,  H01L21/743 ,  H01L21/76254 ,  H01L21/845 ,  H01L27/0203 ,  H01L27/0623 ,  H01L27/0688 ,  H01L27/0694 ,  H01L27/0823 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10802 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/1211 ,  H01L27/2436 ,  H01L29/4236 ,  H01L29/42392 ,  H01L29/66621 ,  H01L29/7841 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L2224/16225 ,  H01L2224/73253

摘要： A method to fabricate a junction-less transistor comprising: forming at least two regions of semiconductor doping; first region with a relatively high level of dopant concentration and second region with at least 1/10 lower dopant concentration, and etching away a portion of said first region for the formation of the transistor gate.

摘要翻译： 一种制造无结型晶体管的方法，包括：形成半导体掺杂的至少两个区域; 具有相对高的掺杂剂浓度水平的第一区域和具有至少1/10较低掺杂剂浓度的第二区域，以及蚀刻掉所述第一区域的一部分以形成晶体管栅极。

公开(公告)号：US08294159B2

公开(公告)日：2012-10-23

申请号：US13073268

申请日：2011-03-28

申请人： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong

发明人： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong

IPC分类号： H01L29/04

CPC分类号： H01L21/76254 ,  H01L21/8221 ,  H01L21/84 ,  H01L23/36 ,  H01L23/481 ,  H01L24/48 ,  H01L25/0657 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01066 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H03K19/177 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method for fabrication of 3D semiconductor devices utilizing a layer transfer and steps for forming transistors on top of a pre-fabricated semiconductor device comprising transistors formed on crystallized semiconductor base layer and metal layer for the transistors interconnections and insulation layer. The advantage of this approach is reduction of the over all metal length used to interconnect the various transistors.

摘要翻译： 一种用于制造利用层转移的三维半导体器件的方法以及用于在预制半导体器件的顶部形成晶体管的步骤，所述预制半导体器件包括形成在晶体化半导体基底层上的晶体管和用于晶体管互连和绝缘层的金属层。 这种方法的优点是减少用于互连各种晶体管的所有金属长度。

公开(公告)号：US08273610B2

公开(公告)日：2012-09-25

申请号：US13273712

申请日：2011-10-14

申请人： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Israel Beinglass ,  Ze'ev Wurman ,  Paul Lim

发明人： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Israel Beinglass ,  Ze'ev Wurman ,  Paul Lim

IPC分类号： H01L21/335 ,  H01L21/8238 ,  H01L21/30

CPC分类号： H01L21/6835 ,  G11C8/16 ,  H01L21/743 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823828 ,  H01L21/84 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/5252 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/10802 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L27/1214 ,  H01L27/1266 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/66901 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/7843 ,  H01L29/7881 ,  H01L29/792 ,  H01L2221/68368 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/83894 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01066 ,  H01L2924/01068 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/12033 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2224/80001 ,  H01L2224/16225 ,  H01L2924/00012

摘要： A method of manufacturing a semiconductor device, the method including, providing a first monocrystalline layer including semiconductor regions, overlaying the first monocrystalline layer with an isolation layer, transferring a second monocrystalline layer comprising semiconductor regions to overlay the isolation layer, wherein the first monocrystalline layer and the second monocrystalline layer are formed from substantially different crystal materials; and subsequently etching the second monocrystalline layer as part of forming at least one transistor in the second monocrystalline layer.

摘要翻译： 一种制造半导体器件的方法，所述方法包括：提供包括半导体区域的第一单晶层，将第一单晶层与隔离层重叠，转移包含半导体区域的第二单晶层覆盖隔离层，其中第一单晶层 并且第二单晶层由基本上不同的晶体材料形成; 随后蚀刻第二单晶层作为在第二单晶层中形成至少一个晶体管的一部分。

公开(公告)号：US20120223436A1

公开(公告)日：2012-09-06

申请号：US13041405

申请日：2011-03-06

申请人： Deepak C. Sekar ,  Zvi Or-Bach ,  Brian Cronquist

发明人： Deepak C. Sekar ,  Zvi Or-Bach ,  Brian Cronquist

IPC分类号： H01L23/34

CPC分类号： H01L23/367 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/00

摘要： A semiconductor device comprising power distribution wires wherein; a portion of said wires have thermal connection to the semiconductor layer and said thermal connection designed to conduct heat but to not conduct electricity.

摘要翻译： 一种包括配电线的半导体器件， 所述导线的一部分具有与半导体层的热连接，并且所述热连接被设计为传导热量但不导电。

公开(公告)号：US20120193719A1

公开(公告)日：2012-08-02

申请号：US12904119

申请日：2010-10-13

申请人： Zvi Or-Bach ,  Brian Cronquist ,  Isreal Beinglass ,  J.L. de Jong ,  Deepak C. Sekar

发明人： Zvi Or-Bach ,  Brian Cronquist ,  Isreal Beinglass ,  J.L. de Jong ,  Deepak C. Sekar

IPC分类号： H01L27/088

CPC分类号： H01L21/6835 ,  H01L21/823431 ,  H01L23/481 ,  H01L23/5283 ,  H01L23/544 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10802 ,  H01L27/10894 ,  H01L27/1108 ,  H01L27/1116 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/2436 ,  H01L27/249 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/7881 ,  H01L29/792 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/10253 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/00

摘要： A device comprising semiconductor memories, the device comprising: a first layer and a second layer of layer-transferred mono-crystallized silicon, wherein the first layer comprises a first plurality of horizontally-oriented transistors; wherein the second layer comprises a second plurality of horizontally-oriented transistors; and wherein the second plurality of horizontally-oriented transistors overlays the first plurality of horizontally-oriented transistors.

摘要翻译： 一种包括半导体存储器的器件，所述器件包括：第一层和第二层转移单结晶硅，其中所述第一层包括第一多个水平取向晶体管; 其中所述第二层包括第二多个水平取向晶体管; 并且其中所述第二多个水平取向晶体管覆盖所述第一多个水平取向晶体管。

公开(公告)号：US08148728B2

公开(公告)日：2012-04-03

申请号：US13073188

申请日：2011-03-28

申请人： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong

发明人： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong

IPC分类号： H01L29/10

CPC分类号： H01L21/76254 ,  H01L21/8221 ,  H01L21/84 ,  H01L23/36 ,  H01L23/481 ,  H01L24/48 ,  H01L25/0657 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01066 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H03K19/177 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method for fabrication of 3D semiconductor devices utilizing a layer transfer and steps for forming transistors on top of a pre-fabricated semiconductor device comprising transistors formed on crystallized semiconductor base layer and metal layer for the transistors interconnections and insulation layer. The advantage of this approach is reduction of the over all metal length used to interconnect the various transistors.

公开(公告)号：US20110049577A1

公开(公告)日：2011-03-03

申请号：US12859665

申请日：2010-08-19

申请人： Zvi Or-Bach ,  Brian Cronquist ,  Israel Beinglass ,  J. L. de Jong ,  Deepak C. Sekar

发明人： Zvi Or-Bach ,  Brian Cronquist ,  Israel Beinglass ,  J. L. de Jong ,  Deepak C. Sekar

IPC分类号： H01L23/52

CPC分类号： H01L21/8221 ,  G03F9/7076 ,  G03F9/7084 ,  H01L21/76254 ,  H01L21/84 ,  H01L23/481 ,  H01L23/544 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11517 ,  H01L27/11551 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L29/78 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/01322 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/80001

摘要： A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.

公开(公告)号：US20130083587A1

公开(公告)日：2013-04-04

申请号：US13251271

申请日：2011-10-02

申请人： Deepak C. Sekar ,  Zvi Or-Bach ,  Paul Lim

发明人： Deepak C. Sekar ,  Zvi Or-Bach ,  Paul Lim

IPC分类号： G11C11/24 ,  G11C11/34

CPC分类号： H01L27/10873 ,  G11C5/025 ,  G11C5/063 ,  G11C11/406 ,  G11C2211/4016 ,  H01L24/16 ,  H01L24/94 ,  H01L27/0203 ,  H01L27/0688 ,  H01L27/10802 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/7841 ,  H01L29/785 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/12033 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2224/81 ,  H01L2924/00

摘要： An Integrated device comprising a first monocrystalline layer comprising logic circuit regions and a second monocrystalline layer comprising memory regions constructed above first monocrystalline layer, wherein the memory regions comprise second transistors, wherein said second transistors comprise drain and source that are horizontally oriented with respect to the second monocrystalline layer, and a multiplicity of vias through the second monocrystalline layer providing connections between the memory regions and the logic circuit regions, wherein at least one of the multiplicity of vias have a radius of less than 100 nm.

摘要翻译： 一种集成装置，包括包括逻辑电路区域的第一单晶层和包括在第一单晶层之上构造的存储区域的第二单晶层，其中所述存储区域包括第二晶体管，其中所述第二晶体管包括相对于所述第一单晶层水平取向的漏极和源极 第二单晶层，以及穿过第二单晶层的多个通孔，提供存储区域和逻辑电路区域之间的连接，其中多个通孔中的至少一个具有小于100nm的半径。

公开(公告)号：US20120094414A1

公开(公告)日：2012-04-19

申请号：US12903847

申请日：2010-10-13

申请人： Zvi Or-Bach ,  Deepak C. Sekar

发明人： Zvi Or-Bach ,  Deepak C. Sekar

IPC分类号： H01L33/00 ,  H01L21/78 ,  H01L31/14

CPC分类号： H01L27/15 ,  H01L25/0756 ,  H01L31/0735 ,  H01L31/1844 ,  H01L33/08 ,  H01L33/382 ,  H01L2924/0002 ,  Y02E10/544 ,  H01L2924/00

摘要： A method for fabricating a light-emitting integrated device, comprises overlying three layers, wherein each of the three layers emits light at a different wavelength, and wherein the overlying comprises one of: performing an atomic species implantation, performing a laser lift-off, performing an etch-back, or chemical-mechanical polishing (CMP).

摘要翻译： 一种制造发光集成装置的方法，包括上述三层，其中三层中的每一层发射不同波长的光，并且其中上覆包括以下之一：执行原子种植入，执行激光剥离， 执行回蚀刻或化学机械抛光（CMP）。

公开(公告)号：US20120231572A1

公开(公告)日：2012-09-13

申请号：US13422049

申请日：2012-03-16

申请人： Zvi Or-Bach ,  Deepak C. Sekar

发明人： Zvi Or-Bach ,  Deepak C. Sekar

IPC分类号： H01L31/18

CPC分类号： H01L27/14605 ,  H01L21/8221 ,  H01L25/0756 ,  H01L27/14612 ,  H01L27/14634 ,  H01L27/153 ,  H01L31/0725 ,  H01L31/1892 ,  H01L33/0079 ,  H01L33/34 ,  H01L2924/0002 ,  Y02E10/50 ,  H01L2924/00

摘要： A method for fabricating an integrated device, the method including, overlying a first crystalline layer onto a second crystalline layer to form a combined layer, wherein one of the first and second crystalline layers is an image sensor layer and at least one of the first and second crystalline layers has been transferred by performing an atomic species implantation, and wherein at least one of the first and second crystalline layers includes single crystal transistors.

摘要翻译： 一种用于制造集成器件的方法，所述方法包括将第一晶体层覆盖到第二晶体层上以形成组合层，其中所述第一和第二晶体层中的一个是图像传感器层，并且所述第一和第二晶体层中的至少一个 通过进行原子物种注入已经转移了第二晶体层，并且其中第一和第二晶体层中的至少一个包括单晶晶体管。