公开(公告)号：US12131108B2

公开(公告)日：2024-10-29

申请号：US18518167

申请日：2023-11-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kenan Yu ,  Qingwen Deng

IPC分类号： G06F30/3312 ,  G06F30/327 ,  G06F30/392 ,  G06F30/394 ,  G06F111/20

CPC分类号： G06F30/3312 ,  G06F30/327 ,  G06F30/392 ,  G06F30/394 ,  G06F2111/20

摘要： A method for providing an IC design is disclosed. The method includes receiving and synthesizing a behavioral description of an IC design; generating, based on the synthesized behavioral description, a layout for the IC design; performing at least a timing analysis on the layout; accessing, based on the timing analysis, a first cell library including a plurality of transistor-based cells, each having one or more transistors and associated with a respective first delay value; accessing, based on the timing analysis, a second cell library including a plurality of non-transistor-based cells, each having no transistor and associated with a respective second delay value; and updating the layout by at least one of inserting one or more of the plurality of transistor-based cells or inserting one or more of the plurality of non-transistor-based cells.

公开(公告)号：US12130548B2

公开(公告)日：2024-10-29

申请号：US18343493

申请日：2023-06-28

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wen-Chang Hsueh ,  Huan-Ling Lee ,  Chia-Jen Chen ,  Hsin-Chang Lee

IPC分类号： G03F1/22 ,  G03F1/24 ,  G03F1/48 ,  G03F1/52 ,  G03F1/58 ,  H01L21/027

CPC分类号： G03F1/22 ,  G03F1/24 ,  G03F1/48 ,  G03F1/52 ,  G03F1/58 ,  H01L21/0274

摘要： A reticle is provided. The reticle includes a first reflective multilayer (ML) over a mask substrate and a capping layer over the first reflective ML. The reticle also includes a first absorption layer over the capping layer and a second reflective multilayer (ML) over the first absorption layer. The reticle further includes an etch stop layer over the second reflective ML and a third reflective multilayer (ML) over the etch stop layer. In addition, the reticle includes an absorption film pair over the third reflective ML.

公开(公告)号：US20240357854A1

公开(公告)日：2024-10-24

申请号：US18763198

申请日：2024-07-03

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yung-Chang Chang ,  Ming Chyi Liu

IPC分类号： H10K50/818 ,  H10K59/122 ,  H10K59/124 ,  H10K59/131 ,  H10K59/35 ,  H10K71/00 ,  H10K71/20 ,  H10K102/00

CPC分类号： H10K50/818 ,  H10K59/122 ,  H10K59/124 ,  H10K59/131 ,  H10K59/35 ,  H10K71/00 ,  H10K71/233 ,  H10K2102/351

摘要： In some embodiments, the present disclosure relates to a device. The device includes an isolation structure disposed over a lower conductor and an additional electrode disposed over the isolation structure. A conductive layer includes a lower horizontal segment disposed on the lower conductor, a vertical segment extending along a sidewall of the isolation structure, and an upper horizontal segment disposed over the isolation structure. The upper horizontal segment has a different thickness than the lower horizontal segment.

公开(公告)号：US20240357829A1

公开(公告)日：2024-10-24

申请号：US18760062

申请日：2024-07-01

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： BO-FENG YOUNG ,  HAN-JONG CHIA ,  SAI-HOOI YEONG ,  YU-MING LIN ,  CHUNG-TE LIN

IPC分类号： H10B51/20 ,  H01L21/768 ,  H01L21/822 ,  H01L23/48 ,  H01L27/06 ,  H01L29/66 ,  H01L29/78 ,  H10B10/00 ,  H10B51/30 ,  H10B51/40

CPC分类号： H10B51/20 ,  H01L21/76898 ,  H01L21/8221 ,  H01L23/481 ,  H01L27/0688 ,  H01L29/66795 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/785 ,  H10B10/12 ,  H10B51/30 ,  H10B51/40

摘要： A semiconductor structure is provided. The semiconductor structure includes a first layer having a logic device; a lower second layer over the first layer; an upper second layer over the lower second layer; a first isolation layer sandwiching by the first layer and the lower second layer; and a plurality of though layer via structures (TLV) penetrating the lower second layer, the upper second layer, the first isolation layer, and the second isolation layer. The lower second layer has a lower memory device. The upper second layer has an upper memory device. A channel length of the upper memory device is longer than a channel length of the lower memory device.

公开(公告)号：US20240357826A1

公开(公告)日：2024-10-24

申请号：US18757483

申请日：2024-06-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chao-I Wu ,  Yu-Ming Lin ,  Sai-Hooi Yeong ,  Han-Jong Chia

IPC分类号： H10B51/10 ,  H01L21/28 ,  H01L23/522 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H10B51/20 ,  H10B51/30

CPC分类号： H10B51/10 ,  H01L23/5226 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/66666 ,  H01L29/78391 ,  H10B51/20 ,  H10B51/30

摘要： Provided are a memory device and a method of forming the same. The memory device includes a first tier on a substrate and a second tier on the first tier. The first tier includes a first layer stack; a first gate electrode penetrating through the first layer stack; a first channel layer between the first layer stack and the first gate electrode; and a first ferroelectric layer between the first channel layer and the first gate electrode. The second tier includes a second layer stack; a second gate electrode penetrating through the second layer stack; a second channel layer between the second layer stack and the second gate electrode; and a second ferroelectric layer between the second channel layer and the second gate electrode.

公开(公告)号：US20240355912A1

公开(公告)日：2024-10-24

申请号：US18761137

申请日：2024-07-01

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  NATIONAL TAIWAN UNIVERSITY

发明人： Ya-Jui TSOU ,  Wei-Jen CHEN ,  Pang-Chun LIU ,  Chee-Wee LIU ,  Shao-Yu LIN ,  Chih-Lin WANG

IPC分类号： H01L29/66

CPC分类号： H01L29/66984

摘要： A memory device comprises a source region, a drain region, a channel region, a gate dielectric layer, an MTJ stack, and a metal gate. The source region and the drain region are over a substrate. The channel region is between the source region and the drain region. The gate dielectric layer is over the channel region. The MTJ stack is over the gate dielectric layer. The MTJ stack comprises a first ferromagnetic layer, a second ferromagnetic layer with a switchable magnetization, and a tunnel barrier layer between the first and second ferromagnetic layers. The metal gate is over the MTJ stack.

公开(公告)号：US20240355899A1

公开(公告)日：2024-10-24

申请号：US18234567

申请日：2023-08-16

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shen-Yang LEE ,  Chun-Da LIAO

IPC分类号： H01L29/51 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC分类号： H01L29/516 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

摘要： Embodiments provide a semiconductor device structure. The structure includes a semiconductor channel layer over a substrate, a gate dielectric layer disposed over the semiconductor channel layer. The gate dielectric layer includes a first high-K (HK) dielectric layer having a first dopant concentration of dipole elements, and a second HK dielectric layer having a second dopant concentration of dipole elements different than the first dopant concentration. The structure also includes a gate electrode layer deposited over the gate dielectric layer, and an insertion layer disposed between the gate dielectric layer and the gate electrode layer, wherein the insertion layer is formed of a noble metal.

公开(公告)号：US20240355843A1

公开(公告)日：2024-10-24

申请号：US18360115

申请日：2023-07-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Po-Chun Liu ,  Yi-Shin Chu ,  Sin-Yi Jiang

IPC分类号： H01L27/146

CPC分类号： H01L27/1461 ,  H01L27/14649 ,  H01L27/14689

摘要： Various embodiments of the present disclosure are directed towards an integrated chip including a substrate comprising a first semiconductor material and a recess in a top surface of the substrate. An absorption structure is disposed within the recess and comprising a second semiconductor material different from the first semiconductor material. The absorption structure has a first doping type. A vertical well region is disposed within the substrate and underlies the absorption structure. The vertical well region has a second doping type different from the first doping type. A liner layer is disposed between the absorption structure and the substrate. The liner layer comprises the second semiconductor material and separates the vertical well region from the absorption structure.

公开(公告)号：US20240355820A1

公开(公告)日：2024-10-24

申请号：US18761135

申请日：2024-07-01

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yu-Lien HUANG

IPC分类号： H01L27/088 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/485 ,  H01L23/528 ,  H01L27/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L27/0886 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5283 ,  H01L27/0694 ,  H01L29/0843 ,  H01L29/66795 ,  H01L29/7851

摘要： An integrated circuit structure includes a lower interconnect structure, a first semiconductor fin, a lower gate structure, first source/drain structures, an upper gate structure, and an upper interconnect structure. The first semiconductor fin is above the lower interconnect structure. The lower gate structure is under the first semiconductor fin and extends across the first semiconductor fin. The first source/drain structures are in the first semiconductor fin and on opposite sides of the lower gate structure. The first source/drain structures forms a lower transistor with the lower gate structure. The upper gate structure is above the first semiconductor fin and extends across the first semiconductor fin. The upper gate structure forms an upper transistor with the first source/drain structures. The upper interconnect structure is above the upper gate.

公开(公告)号：US20240355818A1

公开(公告)日：2024-10-24

申请号：US18758128

申请日：2024-06-28

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Zhi-Chang Lin ,  Huan-Chieh Su ,  Kuo-Cheng Chiang

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L27/0886 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/42392 ,  H01L29/785 ,  H01L29/78696

摘要： Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes a semiconductor fin projecting from a substrate. Semiconductor nanostructures are disposed over the semiconductor fin. A gate electrode is disposed over the semiconductor fin and around the semiconductor nanostructures. A dielectric fin is disposed over the substrate. A dielectric structure is disposed over the dielectric fin. An upper surface of the dielectric structure is disposed over the upper surface of the gate electrode. A dielectric layer is disposed over the substrate. The dielectric fin laterally separates both the gate electrode and the semiconductor nanostructures from the dielectric layer. An upper surface of the dielectric layer is disposed over the upper surface of the gate electrode structure and the upper surface of the dielectric structure. A lower surface of the dielectric layer is disposed below the upper surface of the dielectric fin.