公开(公告)号：US20110298091A1

公开(公告)日：2011-12-08

申请号：US13212541

申请日：2011-08-18

申请人： Hirotoshi Tachibana

发明人： Hirotoshi Tachibana

IPC分类号： H01L29/92

CPC分类号： H01L28/55 ,  H01L27/11504 ,  H01L27/11507

摘要： A capacitor is formed over a semiconductor substrate. The capacitor includes a lower electrode, a capacitor dielectric film and an upper electrode in this order recited, and has an area S equal to or larger than 1000 μm2 and L/S equal to or larger than 0.4 μm−1, where S is an area of a capacitor region in which the lower and upper electrodes face each other across the dielectric film, and L is a total length of a circumference line of the capacitor region.

摘要翻译： 在半导体衬底上形成电容器。 电容器包括下列电极，电容器电介质膜和上部电极，其面积S等于或大于1000μm2，L / S等于或大于0.4μm-1，其中S为 下电极和上电极在电介质膜上彼此面对的电容器区域的面积，L是电容器区域的周长线的总长度。

公开(公告)号：US20110018043A1

公开(公告)日：2011-01-27

申请号：US12563006

申请日：2009-09-18

申请人： Susumu Shuto

发明人： Susumu Shuto

IPC分类号： H01L27/115

CPC分类号： H01L27/11504 ,  H01L27/11507

摘要： A memory includes first contact plugs; ferroelectric capacitors above the first contact plugs; second contact plugs in a first interlayer film being below an area which is between two adjacent ferroelectric capacitors, the second contact plug; first interconnections connected to the second contact plugs, the first interconnections extending in a first direction substantially perpendicular to an arrangement direction, in which the two ferroelectric capacitors are arranged, on the first interlayer film; a second interlayer film above the first interlayer film and the first interconnection; third contact plugs in the second interlayer film, the third contact plugs being respectively connected to the first interconnections at positions shifted from the second contact plugs in the first direction; and second interconnections electrically connecting the third contact plug to the upper electrodes of the two ferroelectric capacitors.

摘要翻译： 存储器包括第一接触插头; 第一接触塞上方的铁电电容器; 第二接触插塞在第一层间膜中，位于两个相邻的铁电电容器之间的区域下方，第二接触插塞; 连接到第二接触插塞的第一互连，第一互连沿第一方向延伸，第一方向基本上垂直于第一层间膜上布置有两个铁电电容器的布置方向; 在第一层间膜上方的第二层间膜和第一互连; 第三接触插塞在第二层间膜中，第三接触插塞在与第二接触插塞沿第一方向偏离的位置处分别连接到第一互连件; 以及将第三接触插塞电连接到两个铁电电容器的上电极的第二互连。

公开(公告)号：US20090243038A1

公开(公告)日：2009-10-01

申请号：US12403371

申请日：2009-03-12

申请人： Kouichi NAGAI ,  Kaoru Saigoh

发明人： Kouichi NAGAI ,  Kaoru Saigoh

IPC分类号： H01L29/92 ,  H01L21/02 ,  H01L21/768 ,  H01L23/48

CPC分类号： H01L24/05 ,  G01R31/2884 ,  H01L24/03 ,  H01L24/06 ,  H01L24/12 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L27/11502 ,  H01L27/11504 ,  H01L27/11509 ,  H01L28/60 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05166 ,  H01L2224/05554 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48463 ,  H01L2224/48764 ,  H01L2224/48766 ,  H01L2224/48864 ,  H01L2224/48866 ,  H01L2224/49175 ,  H01L2224/85 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/19041 ,  Y10S438/957 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45099

摘要： A method of manufacturing a semiconductor device has forming a capacitor having electrodes and a ferroelectric film provided therebetween above a substrate, forming a pad electrode electrically connected to one of the electrodes of the capacitor above the substrate, forming a protective film covering the pad electrode over the substrate, forming an opening in the protective film exposing at least a part of the pad electrode, bringing a measurement terminal into contact with the exposed surface of the pad electrode, etching the surface of the pad electrode after the measurement terminal is brought into contact therewith, and forming a hydrogen absorbing film on the protective film and the pad electrode exposed through the opening.

摘要翻译： 一种半导体器件的制造方法，其特征在于，在基板的上方形成具有电极和铁电体膜的电容器，形成与基板上方的电容器的电极电连接的焊盘电极，形成覆盖焊盘电极的保护膜 所述基板在所述保护膜中形成露出所述焊盘电极的至少一部分的开口，使得测量端子与所述焊盘电极的暴露表面接触，在所述测量端子接触之后蚀刻所述焊盘电极的表面 并且在保护膜和通过开口暴露的焊盘电极上形成吸氢膜。

公开(公告)号：US20090231902A1

公开(公告)日：2009-09-17

申请号：US12401184

申请日：2009-03-10

申请人： Daisaburo Takashima

发明人： Daisaburo Takashima

IPC分类号： G11C11/22 ,  G11C11/24 ,  G11C8/00 ,  G11C11/416

CPC分类号： G11C11/22 ,  G11C5/063 ,  H01L27/11504 ,  H01L27/11507

摘要： A memory includes ferroelectric capacitors; cell transistors each including a drain connected to one electrode of each ferroelectric capacitor, and a gate connected to the word line; and memory cell blocks each including a reset transistor, a block selection transistor, and memory cells including the ferroelectric capacitors and the cell transistors, wherein sources of the cell transistors are connected to the plate lines, the other electrode of the ferroelectric capacitor is connected to one of the sub-bit lines, a source and a drain of the block selection transistor are connected to one of the sub-bit lines and one of the bit lines, a source of the reset transistor is connected to one of the plate lines or a fixed potential, and a drain of the reset transistor in each memory cell block is connected to one of the sub-bit lines, and the memory cell blocks configure a memory cell array.

摘要翻译： 存储器包括铁电电容器; 每个单体晶体管包括连接到每个铁电电容器的一个电极的漏极和连接到该字线的栅极; 以及包括复位晶体管，块选择晶体管和包括铁电电容器和单元晶体管的存储单元的存储单元块，其中单元晶体管的源极连接到板极线，强电介质电容器的另一个电极连接到 子位线之一，块选择晶体管的源极和漏极连接到子位线之一和位线中的一个，复位晶体管的源极连接到板线之一或 每个存储单元块中的复位晶体管的固定电位和漏极连接到一个子位线，并且存储单元块配置存储单元阵列。

公开(公告)号：US20080087928A1

公开(公告)日：2008-04-17

申请号：US11954811

申请日：2007-12-12

申请人： Kouichi NAGAI

发明人： Kouichi NAGAI

IPC分类号： H01L29/94

CPC分类号： H01L28/40 ,  H01L27/105 ,  H01L27/11502 ,  H01L27/11504 ,  H01L27/11507 ,  H01L27/11509 ,  H01L28/55 ,  H01L28/57 ,  H01L43/02

摘要： The semiconductor device according to the present invention comprises a plurality of actually operative capacitors 36a formed, arranged in an actually operative capacitor part 26 over a semiconductor substrate 10 and each including a lower electrode 30, a ferroelectric film 32 and an upper electrode 34; a plurality of dummy capacitors 36b formed, arranged in a dummy capacitor part 28 provided outside of the actually operative capacitor part 26 over the semiconductor substrate 10 and each including the lower electrode 30, the ferroelectric film 32 and the upper electrode 34; a plurality of interconnections 40 respectively formed on said plurality of the actually operative capacitors 36a and respectively connected to the upper electrodes 34 of said plurality of the actually operative capacitors 36a; and the interconnections 40 respectively formed on said plurality of the dummy capacitors 36b, the ratio of the pitch of the dummy capacitors 36b to the pitch of the actually operative capacitors 36a being in the range of 0.9-1.1, and the ratio of the pitch of the interconnections 40 formed over the dummy capacitors 36b to the pitch of the interconnections 40 formed over the actually operative capacitors 36a being in a range of 0.9-1.1.

摘要翻译： 根据本发明的半导体器件包括多个实际操作电容器36a，其形成在半导体衬底10上的实际操作电容器部分26中，并且每个包括下电极30，铁电体膜32和上电极34; 多个虚拟电容器36b，形成在半导体衬底10上，设置在实际操作电容器部分26的外部的虚拟电容器部分28中，并且每个包括下部电极30，铁电体膜32和上部电极34; 分别形成在所述多个实际操作电容器36a上并分别连接到所述多个实际操作电容器3c的上电极34的多个互连40; 以及分别形成在所述多个虚拟电容器36b上的互连40，虚拟电容器36b的间距与实际操作的电容器36a的间距的比率在0.9-1.1的范围内， 形成在虚拟电容器36b上的互连40的间距与形成在实际工作电容器36a上的互连40的间距在0.9-1.1的范围内。

公开(公告)号：US20230422514A1

公开(公告)日：2023-12-28

申请号：US18072180

申请日：2022-11-30

申请人： SK hynix Inc.

发明人： Min Chul SUNG

IPC分类号： H10B53/20 ,  H10B53/10 ,  H10B53/40 ,  H01L23/528

CPC分类号： H01L27/11514 ,  H01L27/11504 ,  H01L27/11509 ,  H01L23/5283

摘要： A semiconductor device includes: a first common plate extending vertically in a first direction; a second common plate which is spaced apart from the first common plate in a second direction and extends vertically in the first direction; a slit formed between the first common plate and the second common plate; a first memory cell array sharing the first common plate and including first capacitors that are vertically stacked in the first direction; and a second memory cell array sharing the second common plate and including second capacitors that are vertically stacked in the first direction.

公开(公告)号：US20180233509A1

公开(公告)日：2018-08-16

申请号：US15434072

申请日：2017-02-16

申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

发明人： Xinshu CAI ,  Khee Yong LIM ,  Kiok Boone Elgin QUEK

IPC分类号： H01L27/11521 ,  H01L21/8234

CPC分类号： H01L27/11521 ,  G11C16/0408 ,  G11C16/0483 ,  G11C16/0491 ,  H01L21/823418 ,  H01L21/823443 ,  H01L27/11504 ,  H01L27/11507 ,  H01L27/11519 ,  H01L27/1156 ,  H01L27/11563 ,  H01L27/11568

摘要： A device and methods for forming the device are disclosed. The method includes providing a substrate prepared with a memory cell region and forming memory cell pairs in the cell region. The memory cell pair comprises of first and second split gate memory cells. Each memory cell includes a first gate serving as an access gate, a second gate adjacent to the first gate, the second gate serving as a storage gate, a first source/drain (S/D) region adjacent to the first gate and a second S/D region adjacent to the second gate. The method also includes forming silicide contacts on the substrate on the gate conductors and first S/D regions and exposed buried common source lines (SLs) in pick-up regions, such that increasing the displacement distance in the wordline and source line (WLSL) region to an extended displacement distance DE avoids shorting between the first offset access gate conductors and adjacent access gate conductors of the rows of memory cell pairs.

公开(公告)号：US09865615B2

公开(公告)日：2018-01-09

申请号：US15170558

申请日：2016-06-01

申请人： SK hynix Inc.

发明人： Nam Jae Lee

IPC分类号： H01L23/522 ,  H01L27/11582 ,  H01L21/768 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11504 ,  H01L29/417

CPC分类号： H01L27/11582 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11504 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/41741

摘要： A semiconductor device includes bit lines extending along a first direction, the bit lines being arranged along a second direction intersecting the first direction, a plurality of channel layers disposed under the bit lines, the plurality of channel layers extending in a third direction perpendicular to a plane extending along the first and second directions and spaced apart along the second direction, so that each channel layer is at least partially overlapped with at least two of the bit lines, and a contact plug extending, from the channel layer, toward one of the bit lines overlapped with the channel layer.

公开(公告)号：US09853027B1

公开(公告)日：2017-12-26

申请号：US15391405

申请日：2016-12-27

申请人： Micron Technology, Inc.

发明人： Werner Juengling

IPC分类号： H01L21/027 ,  H01L21/768 ,  H01L27/088 ,  H01L21/033 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/108 ,  H01L27/11507 ,  H01L27/11504

CPC分类号： H01L27/0886 ,  H01L21/0334 ,  H01L21/823431 ,  H01L27/10826 ,  H01L27/10879 ,  H01L27/11504 ,  H01L27/11507 ,  H01L29/7851 ,  H01L29/7853

摘要： Some embodiments include a method of forming a pattern. A semiconductor substrate has first and second rows extending along a first direction, and which alternate with one another along a second direction. Each of the rows includes course regions that are to be included along patterned structures. The course regions within the first rows are staggered relative to the course regions within the second rows. The patterned structures comprise first segments which extend along a third direction, and comprise second segments which extend along a fourth direction different from the third direction. Patterned masking material is formed across the substrate to define a first pattern having the first segments of the patterned structures, and to define a second pattern having the second segments of the patterned structures. The patterned structures are formed within the first and second patterns defined by the patterned masking material. Some embodiments include apparatuses having finFETs.

公开(公告)号：US09847338B2

公开(公告)日：2017-12-19

申请号：US15447100

申请日：2017-03-01

申请人： ROHM CO., LTD.

发明人： Yuichi Nakao

IPC分类号： H01L21/02 ,  H01L27/11507 ,  H01L21/768 ,  H01L27/11504 ,  H01L49/02 ,  H01L21/32

CPC分类号： H01L27/11507 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/32 ,  H01L21/76849 ,  H01L21/7687 ,  H01L27/11504 ,  H01L28/55 ,  H01L28/57 ,  H01L28/60 ,  H01L28/82

摘要： A semiconductor storage device includes an insulating layer. A ferroelectric capacitor is on the insulating layer and includes a lower electrode, a ferroelectric film, and an upper electrode. An interlayer insulating film is formed on the insulating layer, and has an opening where the ferroelectric capacitor is disposed. A first metal plug is formed in the insulating layer and connected to the lower electrode via the opening. A second metal plug is embedded in the insulating layer outside the ferroelectric capacitor. A hydrogen barrier film covers the ferroelectric capacitor and the interlayer insulating film. An upper surface of the interlayer insulating film is higher than an upper surface of the first metal plug so that a step is therebetween. The lower electrode is formed on the upper surface of the interlayer insulating film, the upper surface of the first metal plug and the step. The upper surface of the interlayer insulating film and the upper surface of the first metal plug are interlinked via a recessed portion of the interlayer insulating film.